Message-ID: <20250611071114.325fb630@fedora.home>
Date: Wed, 11 Jun 2025 07:11:14 +0200
From: Maxime Chevallier <maxime.chevallier@...tlin.com>
To: Sean Anderson <sean.anderson@...ux.dev>
Cc: netdev@...r.kernel.org, Andrew Lunn <andrew+netdev@...n.ch>, "David S .
 Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub
 Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Russell King
 <linux@...linux.org.uk>, Vineeth Karumanchi <vineeth.karumanchi@....com>,
 Heiner Kallweit <hkallweit1@...il.com>, linux-kernel@...r.kernel.org, Kory
 Maincent <kory.maincent@...tlin.com>, Daniel Golle <daniel@...rotopia.org>,
 Simon Horman <horms@...nel.org>, Christian Marangi <ansuelsmth@...il.com>,
 Lei Wei <quic_leiwei@...cinc.com>, Michal Simek <michal.simek@....com>,
 Radhey Shyam Pandey <radhey.shyam.pandey@....com>, Robert Hancock
 <robert.hancock@...ian.com>, linux-arm-kernel@...ts.infradead.org
Subject: Re: [net-next PATCH v6 06/10] net: pcs: Add Xilinx PCS driver

Hi Sean,

I only 

On Tue, 10 Jun 2025 19:31:30 -0400
Sean Anderson <sean.anderson@...ux.dev> wrote:

> This adds support for the Xilinx 1G/2.5G Ethernet PCS/PMA or SGMII device.
> This is a soft device which converts between GMII and either SGMII,
> 1000Base-X, or 2500Base-X. If configured correctly, it can also switch
> between SGMII and 1000BASE-X at runtime. Thoretically this is also possible
> for 2500Base-X, but that requires reconfiguring the serdes. The exact
> capabilities depend on synthesis parameters, so they are read from the
> devicetree.
> 
> This device has a c22-compliant PHY interface, so for the most part we can
> just use the phylink helpers. This device supports an interrupt which is
> triggered on autonegotiation completion. I'm not sure how useful this is,
> since we can never detect a link down (in the PCS).
> 
> This device supports sharing some logic between different implementations
> of the device. In this case, one device contains the "shared logic" and the
> clocks are connected to other devices. To coordinate this, one device
> registers a clock that the other devices can request.  The clock is enabled
> in the probe function by releasing the device from reset. There are no othe
> software controls, so the clock ops are empty.
> 
> Signed-off-by: Sean Anderson <sean.anderson@...ux.dev>
> ---
> 
> Changes in v6:
> - Move axienet_pcs_fixup to AXI Ethernet commit
> - Use an empty statement for next label
> 
> Changes in v5:
> - Export get_phy_c22_id when it is used
> - Expose bind attributes, since there is no issue in doing so
> - Use MDIO_BUS instead of MDIO_DEVICE
> 
> Changes in v4:
> - Re-add documentation for axienet_xilinx_pcs_get that was accidentally
>   removed
> 
> Changes in v3:
> - Adjust axienet_xilinx_pcs_get for changes to pcs_find_fwnode API
> - Call devm_pcs_register instead of devm_pcs_register_provider
> 
> Changes in v2:
> - Add support for #pcs-cells
> - Change compatible to just xlnx,pcs
> - Drop PCS_ALTERA_TSE which was accidentally added while rebasing
> - Rework xilinx_pcs_validate to just clear out half-duplex modes instead
>   of constraining modes based on the interface.
> 
>  MAINTAINERS                  |   6 +
>  drivers/net/pcs/Kconfig      |  22 ++
>  drivers/net/pcs/Makefile     |   2 +
>  drivers/net/pcs/pcs-xilinx.c | 427 +++++++++++++++++++++++++++++++++++
>  drivers/net/phy/phy_device.c |   3 +-
>  include/linux/phy.h          |   1 +
>  6 files changed, 460 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/net/pcs/pcs-xilinx.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 0ac6ba5c40cb..496513837921 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -27060,6 +27060,12 @@ L:	netdev@...r.kernel.org
>  S:	Orphan
>  F:	drivers/net/ethernet/xilinx/ll_temac*
>  
> +XILINX PCS DRIVER
> +M:	Sean Anderson <sean.anderson@...ux.dev>
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/net/xilinx,pcs.yaml
> +F:	drivers/net/pcs/pcs-xilinx.c
> +
>  XILINX PWM DRIVER
>  M:	Sean Anderson <sean.anderson@...o.com>
>  S:	Maintained
> diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
> index f42839a0c332..e0223914362b 100644
> --- a/drivers/net/pcs/Kconfig
> +++ b/drivers/net/pcs/Kconfig
> @@ -52,4 +52,26 @@ config PCS_RZN1_MIIC
>  	  on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
>  	  pass-through mode for MII.
>  
> +config PCS_XILINX
> +	tristate "Xilinx PCS driver"
> +	default XILINX_AXI_EMAC
> +	select COMMON_CLK
> +	select GPIOLIB
> +	select MDIO_BUS
> +	select OF
> +	select PCS
> +	select PHYLINK
> +	help
> +	  PCS driver for the Xilinx 1G/2.5G Ethernet PCS/PMA or SGMII device.
> +	  This device can either act as a PCS+PMA for 1000BASE-X or 2500BASE-X,
> +	  or as a GMII-to-SGMII bridge. It can also switch between 1000BASE-X
> +	  and SGMII dynamically if configured correctly when synthesized.
> +	  Typical applications use this device on an FPGA connected to a GEM or
> +	  TEMAC on the GMII side. The other side is typically connected to
> +	  on-device gigabit transceivers, off-device SERDES devices using TBI,
> +	  or LVDS IO resources directly.
> +
> +	  To compile this driver as a module, choose M here: the module
> +	  will be called pcs-xilinx.
> +
>  endmenu
> diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
> index 35e3324fc26e..347afd91f034 100644
> --- a/drivers/net/pcs/Makefile
> +++ b/drivers/net/pcs/Makefile
> @@ -10,3 +10,5 @@ obj-$(CONFIG_PCS_XPCS)		+= pcs_xpcs.o
>  obj-$(CONFIG_PCS_LYNX)		+= pcs-lynx.o
>  obj-$(CONFIG_PCS_MTK_LYNXI)	+= pcs-mtk-lynxi.o
>  obj-$(CONFIG_PCS_RZN1_MIIC)	+= pcs-rzn1-miic.o
> +obj-$(CONFIG_PCS_ALTERA_TSE)	+= pcs-altera-tse.o

There's something strange going-on here, as pcs-altera-tse was removed
in v6.4 :)

> +obj-$(CONFIG_PCS_XILINX)	+= pcs-xilinx.o

Maxime

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