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Message-ID: <a50c0a9f-1846-4542-97a0-fb9563ed3b3a@collabora.com>
Date: Wed, 11 Jun 2025 11:33:44 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Frank Wunderlich <linux@...web.de>,
MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>, Georgi Djakov <djakov@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Andrew Lunn <andrew@...n.ch>,
Vladimir Oltean <olteanv@...il.com>, "David S. Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Matthias Brugger <matthias.bgg@...il.com>
Cc: Frank Wunderlich <frank-w@...lic-files.de>,
Jia-Wei Chang <jia-wei.chang@...iatek.com>,
Johnson Wang <johnson.wang@...iatek.com>, Arınç ÜNAL
<arinc.unal@...nc9.com>, Landen Chao <Landen.Chao@...iatek.com>,
DENG Qingfang <dqfext@...il.com>, Sean Wang <sean.wang@...iatek.com>,
Daniel Golle <daniel@...rotopia.org>, Lorenzo Bianconi <lorenzo@...nel.org>,
Felix Fietkau <nbd@....name>, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
netdev@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v3 07/13] arm64: dts: mediatek: mt7988: add switch node
Il 08/06/25 23:14, Frank Wunderlich ha scritto:
> From: Frank Wunderlich <frank-w@...lic-files.de>
>
> Add mt7988 builtin mt753x switch nodes.
>
> Signed-off-by: Daniel Golle <daniel@...rotopia.org>
> Signed-off-by: Frank Wunderlich <frank-w@...lic-files.de>
> ---
> v2:
> - drop labels and led-function too (have to be in board)
> ---
> arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 153 ++++++++++++++++++++++
> 1 file changed, 153 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> index ee1e01d720fe..0b35a32b9c89 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> @@ -742,6 +742,159 @@ ethsys: clock-controller@...00000 {
> #reset-cells = <1>;
> };
>
> + switch: switch@...20000 {
> + compatible = "mediatek,mt7988-switch";
> + reg = <0 0x15020000 0 0x8000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
You don't need interrupt-parent, it's already GIC here... :-)
> + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_port0: port@0 {
> + reg = <0>;
Keep it ordered alphabetically - phy-handle (h) before phy-mode (m)
> + phy-mode = "internal";
> + phy-handle = <&gsw_phy0>;
> + };
> +
> + gsw_port1: port@1 {
> + reg = <1>;
> + phy-mode = "internal";
> + phy-handle = <&gsw_phy1>;
> + };
> +
> + gsw_port2: port@2 {
> + reg = <2>;
> + phy-mode = "internal";
> + phy-handle = <&gsw_phy2>;
> + };
> +
> + gsw_port3: port@3 {
> + reg = <3>;
> + phy-mode = "internal";
> + phy-handle = <&gsw_phy3>;
> + };
> +
> + port@6 {
> + reg = <6>;
> + ethernet = <&gmac0>;
> + phy-mode = "internal";
> +
> + fixed-link {
> + speed = <10000>;
> + full-duplex;
> + pause;
> + };
> + };
> + };
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + mediatek,pio = <&pio>;
> +
> + gsw_phy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + interrupts = <0>;
> + phy-mode = "internal";
> + nvmem-cells = <&phy_calibration_p0>;
> + nvmem-cell-names = "phy-cal-data";
phy-mode (p) after nvmem-cell-names (n) please (here and everywhere else)
> +
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_phy0_led0: led@0 {
> + reg = <0>;
> + status = "disabled";
> + };
> +
> + gsw_phy0_led1: led@1 {
> + reg = <1>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + gsw_phy1: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + interrupts = <1>;
> + phy-mode = "internal";
> + nvmem-cells = <&phy_calibration_p1>;
> + nvmem-cell-names = "phy-cal-data";
> +
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_phy1_led0: led@0 {
> + reg = <0>;
> + status = "disabled";
> + };
> +
> + gsw_phy1_led1: led@1 {
> + reg = <1>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + gsw_phy2: ethernet-phy@2 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <2>;
> + interrupts = <2>;
> + phy-mode = "internal";
> + nvmem-cells = <&phy_calibration_p2>;
> + nvmem-cell-names = "phy-cal-data";
> +
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_phy2_led0: led@0 {
> + reg = <0>;
> + status = "disabled";
> + };
> +
> + gsw_phy2_led1: led@1 {
> + reg = <1>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + gsw_phy3: ethernet-phy@3 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <3>;
> + interrupts = <3>;
> + phy-mode = "internal";
> + nvmem-cells = <&phy_calibration_p3>;
> + nvmem-cell-names = "phy-cal-data";
> +
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_phy3_led0: led@0 {
> + reg = <0>;
> + status = "disabled";
> + };
> +
> + gsw_phy3_led1: led@1 {
> + reg = <1>;
> + status = "disabled";
> + };
> + };
> + };
> + };
> + };
> +
> ethwarp: clock-controller@...31000 {
> compatible = "mediatek,mt7988-ethwarp";
> reg = <0 0x15031000 0 0x1000>;
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