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Message-ID: <CAMuHMdW_89naftFMo881zp=7QGJDznFzzqLQ-kLEuyJ=KJWQnA@mail.gmail.com>
Date: Thu, 12 Jun 2025 15:16:45 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Marek Vasut <marek.vasut+renesas@...lbox.org>, Bartosz Golaszewski <brgl@...ev.pl>
Cc: linux-arm-kernel@...ts.infradead.org, 
	Bartosz Golaszewski <bartosz.golaszewski@...aro.org>, Anand Moon <linux.amoon@...il.com>, 
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, Bjorn Helgaas <bhelgaas@...gle.com>, 
	Conor Dooley <conor+dt@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>, 
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org, 
	linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v3 1/3] PCI/pwrctrl: Add optional slot clock to pwrctrl
 driver for PCI slots

On Sat, 7 Jun 2025 at 21:46, Marek Vasut
<marek.vasut+renesas@...lbox.org> wrote:
> Add the ability to enable optional slot clock into the pwrctrl driver.
> This is used to enable slot clock in split-clock topologies, where the
> PCIe host/controller supply and PCIe slot supply are not provided by
> the same clock. The PCIe host/controller clock should be described in
> the controller node as the controller clock, while the slot clock should
> be described in controller bridge/slot subnode.
>
> Example DT snippet:
> &pcicontroller {
>     clocks = <&clk_dif 0>;             /* PCIe controller clock */
>
>     pci@0,0 {
>         #address-cells = <3>;
>         #size-cells = <2>;
>         reg = <0x0 0x0 0x0 0x0 0x0>;
>         compatible = "pciclass,0604";
>         device_type = "pci";
>         clocks = <&clk_dif 1>;         /* PCIe slot clock */
>         vpcie3v3-supply = <&reg_3p3v>;
>         ranges;
>     };
> };
>
> Example clock topology:
>  ____________                    ____________
> |  PCIe host |                  | PCIe slot  |
> |            |                  |            |
> |    PCIe RX<|==================|>PCIe TX    |
> |    PCIe TX<|==================|>PCIe RX    |
> |            |                  |            |
> |   PCIe CLK<|======..  ..======|>PCIe CLK   |
> '------------'      ||  ||      '------------'
>                     ||  ||
>  ____________       ||  ||
> |  9FGV0441  |      ||  ||
> |            |      ||  ||
> |   CLK DIF0<|======''  ||
> |   CLK DIF1<|==========''
> |   CLK DIF2<|
> |   CLK DIF3<|
> '------------'
>
> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> Reviewed-by: Anand Moon <linux.amoon@...il.com>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@...lbox.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>

Bartosz: Any chance you can apply this patch to an immutable branch,
so I can merge that before taking the other two patches?
The alternative is to postpone the DTS patches for one cycle.

Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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