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Message-ID: <5a74859d-5364-475b-992d-62c074f7dcef@lunn.ch>
Date: Thu, 12 Jun 2025 17:33:44 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Oleksij Rempel <o.rempel@...gutronix.de>
Cc: Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
David Jander <david@...tonic.nl>, kernel@...gutronix.de,
linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH net-next v2 1/3] net: phy: dp83tg720: implement soft
reset with asymmetric delay
On Thu, Jun 12, 2025 at 12:41:55PM +0200, Oleksij Rempel wrote:
> From: David Jander <david@...tonic.nl>
>
> Add a .soft_reset callback for the DP83TG720 PHY that issues a hardware
> reset followed by an asymmetric post-reset delay. The delay differs
> based on the PHY's master/slave role to avoid synchronized reset
> deadlocks, which are known to occur when both link partners use
> identical reset intervals.
>
> The delay includes:
> - a fixed 1ms wait to satisfy MDC access timing per datasheet, and
> - an empirically chosen extra delay (97ms for master, 149ms for slave).
>
> Co-developed-by: Oleksij Rempel <o.rempel@...gutronix.de>
> Signed-off-by: David Jander <david@...tonic.nl>
> Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
Reviewed-by: Andrew Lunn <andrew@...n.ch>
Andrew
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