linux-kernel - Re: [PATCH v3 3/7] dt-bindings: interrupt-controller: add MIPS P8700 aclint-sswi

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Message-ID: <20250612-wildfire-ambiance-b4acbe3fff31@spud>
Date: Thu, 12 Jun 2025 16:35:42 +0100
From: Conor Dooley <conor@...nel.org>
To: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
	Anup Patel <anup@...infault.org>,
	Chen Wang <unicorn_wang@...look.com>,
	Inochi Amaoto <inochiama@...il.com>,
	Sunil V L <sunilvl@...tanamicro.com>,
	"Rafael J . Wysocki" <rafael.j.wysocki@...el.com>,
	Ryo Takakura <takakura@...inux.co.jp>, linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
	sophgo@...ts.linux.dev
Subject: Re: [PATCH v3 3/7] dt-bindings: interrupt-controller: add MIPS P8700
 aclint-sswi

On Thu, Jun 12, 2025 at 05:39:07PM +0300, Vladimir Kondratiev wrote:
> Add ACLINT-SSWI variant for the MIPS P8700. This CPU has
> SSWI device compliant with the RISC-V draft spec (see [1])
> CPU indexes on this platform are not contiguous, instead
> it uses bit-fields to encode hart,core,cluster numbers, thus
> property "riscv,hart-indexes" is mandatory
> 
> Link: https://github.com/riscvarchive/riscv-aclint [1]
> 
^ this blank line shouldn't be here fwiw.

> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

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