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Message-ID: <7e4bcfe4-cf79-4b21-865d-a1248e09ffee@linaro.org>
Date: Thu, 12 Jun 2025 16:36:36 +0100
From: James Clark <james.clark@...aro.org>
To: Vladimir Oltean <vladimir.oltean@....com>
Cc: Arnd Bergmann <arnd@...db.de>, Frank Li <Frank.li@....com>,
Vladimir Oltean <olteanv@...il.com>, Mark Brown <broonie@...nel.org>,
linux-spi@...r.kernel.org, imx@...ts.linux.dev, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/4] spi: spi-fsl-dspi: Use non-coherent memory for DMA
On 12/06/2025 3:36 pm, Vladimir Oltean wrote:
> On Thu, Jun 12, 2025 at 03:14:32PM +0100, James Clark wrote:
>>> FWIW, the XSPI FIFO performance should be higher.
>>
>> This leads me to realise a mistake in my original figures. My head was stuck
>> in target mode where we use DMA so I forgot to force DMA in host mode to run
>> the performance tests. The previous figures were all XSPI mode and the small
>> difference in performance could have been just down to the layout of the
>> code changing?
>>
>> Changing it to DMA mode gives figures that make much more sense:
>>
>> Coherent (4096 byte transfers): 6534 kbps
>> Non-coherent: 7347 kbps
>>
>> Coherent (16 byte transfers): 447 kbps
>> Non-coherent: 448 kbps
>>
>>
>> Just for comparison running the same test in XSPI mode:
>>
>> 4096 byte transfers: 2143 kbps
>> 16 byte transfers: 637 kbps
>
> So to be clear, the 'non-coherent' test was done just with patch 2
> applied, or also with 3?
The whole set, and then the non-coherent patch reverted.
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