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Message-ID: <20250612181610.00004a79@huawei.com>
Date: Thu, 12 Jun 2025 18:16:10 +0100
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Terry Bowman <terry.bowman@....com>
CC: <PradeepVineshReddy.Kodamati@....com>, <dave@...olabs.net>,
<dave.jiang@...el.com>, <alison.schofield@...el.com>,
<vishal.l.verma@...el.com>, <ira.weiny@...el.com>,
<dan.j.williams@...el.com>, <bhelgaas@...gle.com>, <bp@...en8.de>,
<ming.li@...omail.com>, <shiju.jose@...wei.com>, <dan.carpenter@...aro.org>,
<Smita.KoralahalliChannabasappa@....com>, <kobayashi.da-06@...itsu.com>,
<yanfei.xu@...el.com>, <rrichter@....com>, <peterz@...radead.org>,
<colyli@...e.de>, <uaisheng.ye@...el.com>,
<fabio.m.de.francesco@...ux.intel.com>, <ilpo.jarvinen@...ux.intel.com>,
<yazen.ghannam@....com>, <linux-cxl@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>
Subject: Re: [PATCH v9 14/16] cxl/pci: Remove unnecessary CXL Endpoint
handling helper functions
On Tue, 3 Jun 2025 12:22:37 -0500
Terry Bowman <terry.bowman@....com> wrote:
> The CXL driver's cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras()
> are unnecessary helper functions used only for Endpoints. Remove these
> functions as they are not common for all CXL devices and do not provide
> value for EP handling.
>
> Rename __cxl_handle_ras to cxl_handle_ras() and __cxl_handle_cor_ras()
> to cxl_handle_cor_ras().
>
> Signed-off-by: Terry Bowman <terry.bowman@....com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@...wei.com>
If it looks like we are going to need a few more versions, maybe
drag this to front so Dave can pick it up and reduce size of the
patch set? This one is a good cleanup on it's own.
> ---
> drivers/cxl/core/pci.c | 32 ++++++++++++--------------------
> 1 file changed, 12 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index b6836825e8df..b36a58607041 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -664,8 +664,8 @@ void read_cdat_data(struct cxl_port *port)
> }
> EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL");
>
> -static void __cxl_handle_cor_ras(struct device *dev, u64 serial,
> - void __iomem *ras_base)
> +static void cxl_handle_cor_ras(struct device *dev, u64 serial,
> + void __iomem *ras_base)
> {
> void __iomem *addr;
> u32 status;
> @@ -684,11 +684,6 @@ static void __cxl_handle_cor_ras(struct device *dev, u64 serial,
> trace_cxl_aer_correctable_error(dev, serial, status);
> }
>
> -static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds)
> -{
> - return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras);
> -}
> -
> /* CXL spec rev3.0 8.2.4.16.1 */
> static void header_log_copy(void __iomem *ras_base, u32 *log)
> {
> @@ -710,8 +705,8 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)
> * Log the state of the RAS status registers and prepare them to log the
> * next error status. Return 1 if reset needed.
> */
> -static pci_ers_result_t __cxl_handle_ras(struct device *dev, u64 serial,
> - void __iomem *ras_base)
> +static pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial,
> + void __iomem *ras_base)
> {
> u32 hl[CXL_HEADERLOG_SIZE_U32];
> void __iomem *addr;
> @@ -746,11 +741,6 @@ static pci_ers_result_t __cxl_handle_ras(struct device *dev, u64 serial,
> return PCI_ERS_RESULT_PANIC;
> }
>
> -static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
> -{
> - return __cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, cxlds->regs.ras);
> -}
> -
> #ifdef CONFIG_PCIEAER_CXL
>
> static void __iomem *cxl_get_ras_base(struct device *dev)
> @@ -802,7 +792,7 @@ void cxl_port_cor_error_detected(struct device *dev)
> {
> void __iomem *ras_base = cxl_get_ras_base(dev);
>
> - __cxl_handle_cor_ras(dev, 0, ras_base);
> + cxl_handle_cor_ras(dev, 0, ras_base);
> }
> EXPORT_SYMBOL_NS_GPL(cxl_port_cor_error_detected, "CXL");
>
> @@ -810,20 +800,20 @@ pci_ers_result_t cxl_port_error_detected(struct device *dev)
> {
> void __iomem *ras_base = cxl_get_ras_base(dev);
>
> - return __cxl_handle_ras(dev, 0, ras_base);
> + return cxl_handle_ras(dev, 0, ras_base);
> }
> EXPORT_SYMBOL_NS_GPL(cxl_port_error_detected, "CXL");
>
> static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds,
> struct cxl_dport *dport)
> {
> - return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, dport->regs.ras);
> + return cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, dport->regs.ras);
> }
>
> static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds,
> struct cxl_dport *dport)
> {
> - return __cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, dport->regs.ras);
> + return cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, dport->regs.ras);
> }
>
> /*
> @@ -921,7 +911,8 @@ void cxl_cor_error_detected(struct device *dev)
> if (cxlds->rcd)
> cxl_handle_rdport_errors(cxlds);
>
> - cxl_handle_endpoint_cor_ras(cxlds);
> + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial,
> + cxlds->regs.ras);
> }
> }
> EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL");
> @@ -958,7 +949,8 @@ pci_ers_result_t cxl_error_detected(struct device *dev)
> * chance the situation is recoverable dump the status of the RAS
> * capability registers and bounce the active state of the memdev.
> */
> - ue = cxl_handle_endpoint_ras(cxlds);
> + ue = cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial,
> + cxlds->regs.ras);
> }
>
> return ue;
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