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Message-ID: <aEsQKeJGOlCooOUK@debug.ba.rivosinc.com>
Date: Thu, 12 Jun 2025 10:36:41 -0700
From: Deepak Gupta <debug@...osinc.com>
To: Chunyan Zhang <zhang.lyra@...il.com>
Cc: Chunyan Zhang <zhangchunyan@...as.ac.cn>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Andrew Morton <akpm@...ux-foundation.org>,
Alexandre Ghiti <alex@...ti.fr>, Ved Shanbhogue <ved@...osinc.com>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH RFC v7 2/3] riscv: mm: Add soft-dirty page tracking
support
On Thu, Jun 12, 2025 at 02:51:57PM +0800, Chunyan Zhang wrote:
>Hi Deepak,
>
>On Sat, 7 Jun 2025 at 01:24, Deepak Gupta <debug@...osinc.com> wrote:
>>
>> On Wed, Apr 09, 2025 at 05:53:19PM +0800, Chunyan Zhang wrote:
>> >The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
>> >for software, this patch uses bit 59 for soft-dirty.
>> >
>> >To add swap PTE soft-dirty tracking, we borrow bit 3 which is available
>> >for swap PTEs on RISC-V systems.
>> >
>> >Signed-off-by: Chunyan Zhang <zhangchunyan@...as.ac.cn>
>> >---
>> > arch/riscv/Kconfig | 1 +
>> > arch/riscv/include/asm/pgtable-bits.h | 19 +++++++
>> > arch/riscv/include/asm/pgtable.h | 71 ++++++++++++++++++++++++++-
>> > 3 files changed, 89 insertions(+), 2 deletions(-)
>> >
>> >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> >index 332fc00243ad..652e2bbfb702 100644
>> >--- a/arch/riscv/Kconfig
>> >+++ b/arch/riscv/Kconfig
>> >@@ -139,6 +139,7 @@ config RISCV
>> > select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
>> > select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
>> > select HAVE_ARCH_SECCOMP_FILTER
>> >+ select HAVE_ARCH_SOFT_DIRTY if 64BIT && MMU && RISCV_ISA_SVRSW60T59B
>> > select HAVE_ARCH_STACKLEAK
>> > select HAVE_ARCH_THREAD_STRUCT_WHITELIST
>> > select HAVE_ARCH_TRACEHOOK
>> >diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
>> >index a8f5205cea54..a6fa871dc19e 100644
>> >--- a/arch/riscv/include/asm/pgtable-bits.h
>> >+++ b/arch/riscv/include/asm/pgtable-bits.h
>> >@@ -20,6 +20,25 @@
>> >
>> > #define _PAGE_SPECIAL (1 << 8) /* RSW: 0x1 */
>> > #define _PAGE_DEVMAP (1 << 9) /* RSW, devmap */
>> >+
>> >+#ifdef CONFIG_MEM_SOFT_DIRTY
>> >+
>> >+/* ext_svrsw60t59b: bit 59 for software dirty tracking */
>> >+#define _PAGE_SOFT_DIRTY \
>> >+ ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \
>> >+ (1UL << 59) : 0)
>> >+/*
>> >+ * Bit 3 is always zero for swap entry computation, so we
>> >+ * can borrow it for swap page soft-dirty tracking.
>> >+ */
>> >+#define _PAGE_SWP_SOFT_DIRTY \
>> >+ ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \
>> >+ _PAGE_EXEC : 0)
>> >+#else
>> >+#define _PAGE_SOFT_DIRTY 0
>> >+#define _PAGE_SWP_SOFT_DIRTY 0
>> >+#endif /* CONFIG_MEM_SOFT_DIRTY */
>> >+
>>
>> Above can be done like this
>>
>> +
>> +#ifdef CONFIG_MEM_SOFT_DIRTY && RISCV_ISA_EXT_SVRSW60T59B
>> +
>> +/* ext_svrsw60t59b: bit 59 for software dirty tracking */
>> +#define _PAGE_SOFT_DIRTY (1UL << 59)
>> +/*
>> + * Bit 3 is always zero for swap entry computation, so we
>> + * can borrow it for swap page soft-dirty tracking.
>> + */
>> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_EXEC
>> +#else
>> +#define _PAGE_SOFT_DIRTY 0
>> +#define _PAGE_SWP_SOFT_DIRTY 0
>> +#endif /* CONFIG_MEM_SOFT_DIRTY */
>>
>
>No, the feature depends not only on the compile-time configuration but
>also on the run-time environment.
>
>We need to check if the platform on which the system is running
>supports the extension SVRSW60T59B, and riscv_has_extension_unlikely()
>does that check that is a run-time check, not a build-time condition.
>
aah you are right. Ignore my comment.
>> > #define _PAGE_TABLE _PAGE_PRESENT
>> >
>> > /*
>> >diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>> >index 428e48e5f57d..14461ffe6321 100644
>> >--- a/arch/riscv/include/asm/pgtable.h
>> >+++ b/arch/riscv/include/asm/pgtable.h
>> >@@ -436,7 +436,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>>
>> Shouldn't "static inline int pte_dirty(pte_t pte)" be updated as well
>
>It may not be needed, since pte_dirty() on X86 and ARM doesn't check
>_PAGE_SOFT_DIRTY either.
arch/arm64/include/asm/pgtable.h
#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
`pte_sw_dirty` eventually expands to checking of b55 which is soft dirty.
But when I look at `pte_to_pagemap_entry` (`fs/proc/task_mmu.c`), I don't
see that pte to pagemap entry conversion for arm64. There is no equivalent
`pte_soft_dirty` macro defined on arm64.
Yeah may be it's not needed then.
>
>Thanks for the review,
>Chunyan
>
>
>
>
>>
>> static inline int pte_dirty(pte_t pte)
>> {
>> return pte_val(pte) & (_PAGE_DIRTY | _PAGE_SOFT_DIRTY);
>> }
>>
>> Perhaps have a macro which includes both dirty together and then use together.
>>
>>
>> >
>> > static inline pte_t pte_mkdirty(pte_t pte)
>> > {
>> >- return __pte(pte_val(pte) | _PAGE_DIRTY);
>> >+ return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
>> > }
>> >
>> > static inline pte_t pte_mkclean(pte_t pte)
>> >@@ -469,6 +469,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
>> > return pte;
>> > }
>> >
>> >+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>> >+static inline bool pte_soft_dirty(pte_t pte)
>> >+{
>> >+ return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
>> >+}
>> >+
>> >+static inline pte_t pte_mksoft_dirty(pte_t pte)
>> >+{
>> >+ return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
>> >+}
>> >+
>> >+static inline pte_t pte_clear_soft_dirty(pte_t pte)
>> >+{
>> >+ return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
>> >+}
>> >+
>> >+static inline bool pte_swp_soft_dirty(pte_t pte)
>> >+{
>> >+ return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
>> >+}
>> >+
>> >+static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
>> >+{
>> >+ return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
>> >+}
>> >+
>> >+static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
>> >+{
>> >+ return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
>> >+}
>> >+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>> >+
>> > #ifdef CONFIG_RISCV_ISA_SVNAPOT
>> > #define pte_leaf_size(pte) (pte_napot(pte) ? \
>> > napot_cont_size(napot_cont_order(pte)) :\
>> >@@ -821,6 +853,40 @@ static inline pud_t pud_mkspecial(pud_t pud)
>> > }
>> > #endif
>> >
>> >+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>> >+static inline bool pmd_soft_dirty(pmd_t pmd)
>> >+{
>> >+ return pte_soft_dirty(pmd_pte(pmd));
>> >+}
>> >+
>> >+static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
>> >+{
>> >+ return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
>> >+}
>> >+
>> >+static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
>> >+{
>> >+ return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
>> >+}
>> >+
>> >+#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
>> >+static inline bool pmd_swp_soft_dirty(pmd_t pmd)
>> >+{
>> >+ return pte_swp_soft_dirty(pmd_pte(pmd));
>> >+}
>> >+
>> >+static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
>> >+{
>> >+ return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
>> >+}
>> >+
>> >+static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
>> >+{
>> >+ return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
>> >+}
>> >+#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
>> >+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>> >+
>> > static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
>> > pmd_t *pmdp, pmd_t pmd)
>> > {
>> >@@ -910,7 +976,8 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
>> > *
>> > * Format of swap PTE:
>> > * bit 0: _PAGE_PRESENT (zero)
>> >- * bit 1 to 3: _PAGE_LEAF (zero)
>> >+ * bit 1 to 2: (zero)
>> >+ * bit 3: _PAGE_SWP_SOFT_DIRTY
>> > * bit 5: _PAGE_PROT_NONE (zero)
>> > * bit 6: exclusive marker
>> > * bits 7 to 11: swap type
>> >--
>> >2.34.1
>> >
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