linux-kernel - Re: [PATCH] clk: renesas: rzv2h-cpg: Fix missing CLK_SET_RATE

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Message-ID: <CA+V-a8sgqzs_7RKN1SdKTWMrzg2xE7JbmKxkQSD0Tn4YDawAmg@mail.gmail.com>
Date: Thu, 12 Jun 2025 20:23:01 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH] clk: renesas: rzv2h-cpg: Fix missing CLK_SET_RATE_PARENT
 flag for ddiv clocks

Hi Geert,

Thank you for the review.

On Thu, Jun 12, 2025 at 2:48 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 9 Jun 2025 at 16:03, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Commit bc4d25fdfadf ("clk: renesas: rzv2h: Add support for dynamic
> > switching divider clocks") missed setting the `CLK_SET_RATE_PARENT`
> > flag when registering ddiv clocks.
> >
> > Without this flag, rate changes to the divider clock do not propagate
> > to its parent, potentially resulting in incorrect clock configurations.
> >
> > Fix this by setting `CLK_SET_RATE_PARENT` in the clock init data.
> >
> > Fixes: bc4d25fdfadfa ("clk: renesas: rzv2h: Add support for dynamic switching divider clocks")
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> i.e. will queue in renesas-clk for v6.17, unless you think it deserves
> to be fast-tracked as a fix (issue present since v6.12).
>
I think we can live with this being applied to v6.17. I noticed this
only when adding XSPI support.

Cheers,
Prabhakar