linux-kernel - Re: [PATCH v6] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks

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Message-ID: <174970084199.547582.700390478777102209.b4-ty@kernel.org>
Date: Wed, 11 Jun 2025 23:00:40 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	linux-arm-msm@...r.kernel.org,
	linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: stable@...r.kernel.org,
	Abhinav Kumar <quic_abhinavk@...cinc.com>,
	Dmitry Baryshkov <lumag@...nel.org>
Subject: Re: [PATCH v6] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks


On Tue, 20 May 2025 11:07:42 +0200, Krzysztof Kozlowski wrote:
> On SM8750 the setting rate of pixel and byte clocks, while the parent
> DSI PHY PLL, fails with:
> 
>   disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.
> 
> DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in
> CMN_CTRL_0 asserted.
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks
      commit: 0acf9e65a47d1e489c8b24c45a64436e30bcccf4

Best regards,
-- 
Bjorn Andersson <andersson@...nel.org>