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Message-ID: <202506121258.qVeeEKfy-lkp@intel.com>
Date: Thu, 12 Jun 2025 12:43:29 +0800
From: kernel test robot <lkp@...el.com>
To: Hans Zhang <18255117159@....com>, lpieralisi@...nel.org,
bhelgaas@...gle.com, mani@...nel.org, kwilczynski@...nel.org
Cc: oe-kbuild-all@...ts.linux.dev, robh@...nel.org, jingoohan1@...il.com,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
Hans Zhang <18255117159@....com>
Subject: Re: [PATCH 13/13] PCI: dwc: Refactor tegra194 to use
dw_pcie_clear_and_set_dword()
Hi Hans,
kernel test robot noticed the following build warnings:
[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus linus/master v6.16-rc1 next-20250611]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Hans-Zhang/PCI-dwc-Refactor-dwc-to-use-dw_pcie_clear_and_set_dword/20250612-003548
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20250611163227.861403-1-18255117159%40163.com
patch subject: [PATCH 13/13] PCI: dwc: Refactor tegra194 to use dw_pcie_clear_and_set_dword()
config: x86_64-buildonly-randconfig-003-20250612 (https://download.01.org/0day-ci/archive/20250612/202506121258.qVeeEKfy-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250612/202506121258.qVeeEKfy-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202506121258.qVeeEKfy-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/pci/controller/dwc/pcie-tegra194.c: In function 'tegra_pcie_dw_host_init':
>> drivers/pci/controller/dwc/pcie-tegra194.c:884:13: warning: unused variable 'val' [-Wunused-variable]
884 | u32 val;
| ^~~
vim +/val +884 drivers/pci/controller/dwc/pcie-tegra194.c
56e15a238d9278 Vidya Sagar 2019-08-13 879
64451ac83fe6ab Bjorn Helgaas 2022-08-04 880 static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
56e15a238d9278 Vidya Sagar 2019-08-13 881 {
56e15a238d9278 Vidya Sagar 2019-08-13 882 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
f1ab409d578752 Vidya Sagar 2022-07-21 883 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
56e15a238d9278 Vidya Sagar 2019-08-13 @884 u32 val;
56e15a238d9278 Vidya Sagar 2019-08-13 885
275e88b06a277c Rob Herring 2020-12-18 886 pp->bridge->ops = &tegra_pci_ops;
275e88b06a277c Rob Herring 2020-12-18 887
369b868f4a2ef8 Vidya Sagar 2020-11-26 888 if (!pcie->pcie_cap_base)
369b868f4a2ef8 Vidya Sagar 2020-11-26 889 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
369b868f4a2ef8 Vidya Sagar 2020-11-26 890 PCI_CAP_ID_EXP);
369b868f4a2ef8 Vidya Sagar 2020-11-26 891
9891c2a48c49a9 Hans Zhang 2025-06-12 892 dw_pcie_clear_and_set_dword(pci, PCI_IO_BASE,
9891c2a48c49a9 Hans Zhang 2025-06-12 893 IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8, 0);
56e15a238d9278 Vidya Sagar 2019-08-13 894
9891c2a48c49a9 Hans Zhang 2025-06-12 895 dw_pcie_clear_and_set_dword(pci, PCI_PREF_MEMORY_BASE, 0,
9891c2a48c49a9 Hans Zhang 2025-06-12 896 CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE |
9891c2a48c49a9 Hans Zhang 2025-06-12 897 CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE);
56e15a238d9278 Vidya Sagar 2019-08-13 898
56e15a238d9278 Vidya Sagar 2019-08-13 899 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
56e15a238d9278 Vidya Sagar 2019-08-13 900
87f10faf166a91 Bjorn Helgaas 2024-08-27 901 /* Enable as 0xFFFF0001 response for RRS */
9891c2a48c49a9 Hans Zhang 2025-06-12 902 dw_pcie_clear_and_set_dword(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT,
9891c2a48c49a9 Hans Zhang 2025-06-12 903 AMBA_ERROR_RESPONSE_RRS_MASK << AMBA_ERROR_RESPONSE_RRS_SHIFT,
9891c2a48c49a9 Hans Zhang 2025-06-12 904 AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 <<
87f10faf166a91 Bjorn Helgaas 2024-08-27 905 AMBA_ERROR_RESPONSE_RRS_SHIFT);
56e15a238d9278 Vidya Sagar 2019-08-13 906
a54e190737181c Vidya Sagar 2022-07-21 907 /* Clear Slot Clock Configuration bit if SRNS configuration */
9891c2a48c49a9 Hans Zhang 2025-06-12 908 if (pcie->enable_srns)
9891c2a48c49a9 Hans Zhang 2025-06-12 909 dw_pcie_clear_and_set_dword(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
9891c2a48c49a9 Hans Zhang 2025-06-12 910 PCI_EXP_LNKSTA_SLC, 0);
a54e190737181c Vidya Sagar 2022-07-21 911
56e15a238d9278 Vidya Sagar 2019-08-13 912 config_gen3_gen4_eq_presets(pcie);
56e15a238d9278 Vidya Sagar 2019-08-13 913
56e15a238d9278 Vidya Sagar 2019-08-13 914 init_host_aspm(pcie);
56e15a238d9278 Vidya Sagar 2019-08-13 915
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 916 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 917 if (!pcie->supports_clkreq) {
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 918 disable_aspm_l11(pcie);
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 919 disable_aspm_l12(pcie);
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 920 }
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 921
9891c2a48c49a9 Hans Zhang 2025-06-12 922 if (!pcie->of_data->has_l1ss_exit_fix)
9891c2a48c49a9 Hans Zhang 2025-06-12 923 dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF,
9891c2a48c49a9 Hans Zhang 2025-06-12 924 GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0);
56e15a238d9278 Vidya Sagar 2019-08-13 925
9891c2a48c49a9 Hans Zhang 2025-06-12 926 if (pcie->update_fc_fixup)
9891c2a48c49a9 Hans Zhang 2025-06-12 927 dw_pcie_clear_and_set_dword(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF,
9891c2a48c49a9 Hans Zhang 2025-06-12 928 0, 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT);
56e15a238d9278 Vidya Sagar 2019-08-13 929
56e15a238d9278 Vidya Sagar 2019-08-13 930 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
56e15a238d9278 Vidya Sagar 2019-08-13 931
275e88b06a277c Rob Herring 2020-12-18 932 return 0;
275e88b06a277c Rob Herring 2020-12-18 933 }
275e88b06a277c Rob Herring 2020-12-18 934
--
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