linux-kernel - RE: [PATCH v1 07/12] iommu/arm-smmu-v3: Implement arm_smmu_get_viommu_size and arm_vsmmu

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Message-ID: <BN9PR11MB52764E40612C1293699E43F98C74A@BN9PR11MB5276.namprd11.prod.outlook.com>
Date: Thu, 12 Jun 2025 08:20:30 +0000
From: "Tian, Kevin" <kevin.tian@...el.com>
To: Nicolin Chen <nicolinc@...dia.com>, "jgg@...dia.com" <jgg@...dia.com>
CC: "will@...nel.org" <will@...nel.org>, "robin.murphy@....com"
	<robin.murphy@....com>, "joro@...tes.org" <joro@...tes.org>,
	"ddutile@...hat.com" <ddutile@...hat.com>, "Liu, Yi L" <yi.l.liu@...el.com>,
	"peterz@...radead.org" <peterz@...radead.org>, "jsnitsel@...hat.com"
	<jsnitsel@...hat.com>, "praan@...gle.com" <praan@...gle.com>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "iommu@...ts.linux.dev"
	<iommu@...ts.linux.dev>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "patches@...ts.linux.dev"
	<patches@...ts.linux.dev>, "baolu.lu@...ux.intel.com"
	<baolu.lu@...ux.intel.com>
Subject: RE: [PATCH v1 07/12] iommu/arm-smmu-v3: Implement
 arm_smmu_get_viommu_size and arm_vsmmu_init

> From: Nicolin Chen <nicolinc@...dia.com>
> Sent: Tuesday, June 10, 2025 1:14 AM
> 
> +int arm_smmu_get_viommu_size(enum iommu_viommu_type
> viommu_type,
> +			     struct device *dev, size_t *viommu_size)
> +{
> +	struct arm_smmu_master *master = dev_iommu_priv_get(dev);
> +	struct arm_smmu_device *smmu = master->smmu;
> +
> +	if (!(smmu->features & ARM_SMMU_FEAT_NESTING))
> +		return -EOPNOTSUPP;
> +
> +	/*
> +	 * FORCE_SYNC is not set with FEAT_NESTING. Some study of the
> exact HW
> +	 * defect is needed to determine if arm_vsmmu_cache_invalidate()
> needs
> +	 * any change to remove this.
> +	 */
> +	if (WARN_ON(smmu->options &
> ARM_SMMU_OPT_CMDQ_FORCE_SYNC))
> +		return -EOPNOTSUPP;
> +
> +	/*
> +	 * Must support some way to prevent the VM from bypassing the
> cache
> +	 * because VFIO currently does not do any cache maintenance.
> canwbs
> +	 * indicates the device is fully coherent and no cache maintenance is
> +	 * ever required, even for PCI No-Snoop. S2FWB means the S1 can't
> make
> +	 * things non-coherent using the memattr, but No-Snoop behavior is
> not
> +	 * effected.
> +	 */
> +	if (!arm_smmu_master_canwbs(master) &&
> +	    !(smmu->features & ARM_SMMU_FEAT_S2FWB))
> +		return -EOPNOTSUPP;
> +
> +	if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3)
> +		return -EOPNOTSUPP;

it's more intuitive to check it first.

btw does it make sense to also add below here?
	if (s2_parent->smmu != master->smmu)
		return ERR_PTR(-EINVAL);