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Message-Id: <20250613134943.3186517-12-kan.liang@linux.intel.com>
Date: Fri, 13 Jun 2025 06:49:42 -0700
From: kan.liang@...ux.intel.com
To: peterz@...radead.org,
mingo@...hat.com,
acme@...nel.org,
namhyung@...nel.org,
tglx@...utronix.de,
dave.hansen@...ux.intel.com,
irogers@...gle.com,
adrian.hunter@...el.com,
jolsa@...nel.org,
alexander.shishkin@...ux.intel.com,
linux-kernel@...r.kernel.org
Cc: dapeng1.mi@...ux.intel.com,
ak@...ux.intel.com,
zide.chen@...el.com,
Kan Liang <kan.liang@...ux.intel.com>
Subject: [RFC PATCH 11/12] perf/x86: Add SSP in extended regs
From: Kan Liang <kan.liang@...ux.intel.com>
Support SSP as the extended registers. It can be configured in the
sample_ext_regs_intr/user.
Only the PMU with PERF_PMU_CAP_EXTENDED_REGS2 supports the feature.
The value can be retrieved via the XSAVES.
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
---
arch/x86/events/core.c | 7 +++++++
arch/x86/events/perf_event.h | 5 +++++
arch/x86/include/asm/perf_event.h | 1 +
arch/x86/include/uapi/asm/perf_regs.h | 6 +++++-
arch/x86/kernel/perf_regs.c | 5 +++++
5 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 9bcef9a32dd2..65e4460fdc28 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -441,6 +441,8 @@ static void x86_pmu_get_ext_regs(struct x86_perf_regs *perf_regs, u64 mask)
sizeof(struct avx_512_zmm_uppers_state));
__x86_pmu_get_regs(XFEATURE_MASK_Hi16_ZMM, perf_regs->h16zmm_regs,
sizeof(struct avx_512_hi16_state));
+ __x86_pmu_get_regs(XFEATURE_MASK_CET_USER, perf_regs->cet_regs,
+ sizeof(struct cet_user_state));
}
static void release_ext_regs_buffers(void)
@@ -476,6 +478,8 @@ static void reserve_ext_regs_buffers(void)
size += sizeof(struct avx_512_zmm_uppers_state);
if (x86_pmu.ext_regs_mask & BIT_ULL(X86_EXT_REGS_H16ZMM))
size += sizeof(struct avx_512_hi16_state);
+ if (x86_pmu.ext_regs_mask & BIT_ULL(X86_EXT_REGS_CET))
+ size += sizeof(struct cet_user_state);
/* XSAVE feature requires 64-byte alignment. */
size += 64;
@@ -757,6 +761,7 @@ int x86_pmu_hw_config(struct perf_event *event)
check_ext_regs(X86_EXT_REGS_OPMASK);
check_ext_regs(X86_EXT_REGS_ZMMH);
check_ext_regs(X86_EXT_REGS_H16ZMM);
+ check_ext_regs(X86_EXT_REGS_CET);
}
}
return x86_setup_perfctr(event);
@@ -1866,6 +1871,8 @@ void x86_pmu_setup_regs_data(struct perf_event *event,
XFEATURE_MASK_ZMM_Hi256, PERF_X86_EXT_REG_ZMMH_SIZE);
init_ext_regs_data(X86_EXT_REGS_H16ZMM, perf_regs->h16zmm_regs,
XFEATURE_MASK_Hi16_ZMM, PERF_X86_EXT_REG_H16ZMM_SIZE);
+ init_ext_regs_data(X86_EXT_REGS_CET, perf_regs->cet_regs,
+ XFEATURE_MASK_CET_USER, PERF_X86_EXT_REG_SSP_SIZE);
mask &= ~ignore_mask;
if (mask)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 93a65c529afe..e4906c0b33da 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -694,6 +694,7 @@ enum {
X86_EXT_REGS_OPMASK,
X86_EXT_REGS_ZMMH,
X86_EXT_REGS_H16ZMM,
+ X86_EXT_REGS_CET,
};
#define PERF_PEBS_DATA_SOURCE_MAX 0x100
@@ -1345,6 +1346,10 @@ static inline int get_num_ext_regs(u64 *ext_regs, unsigned int type)
mask = GENMASK_ULL(PERF_REG_X86_EXT_REGS_64, PERF_REG_X86_ZMM16);
mask2 = GENMASK_ULL(PERF_REG_X86_ZMM31 - 64, 0);
return hweight64(ext_regs[0] & mask) + hweight64(ext_regs[1] & mask2);
+ case X86_EXT_REGS_CET:
+ if (ext_regs[1] & BIT_ULL(PERF_REG_X86_SSP - 64))
+ return 1;
+ return 0;
default:
return 0;
}
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index eb35ba9afbb4..e49a26886e64 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -598,6 +598,7 @@ struct x86_perf_regs {
u64 *opmask_regs;
u64 *zmmh_regs;
u64 *h16zmm_regs;
+ u64 *cet_regs;
};
extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs);
diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h
index c43a025b0c01..82df5c65d701 100644
--- a/arch/x86/include/uapi/asm/perf_regs.h
+++ b/arch/x86/include/uapi/asm/perf_regs.h
@@ -138,8 +138,11 @@ enum perf_event_x86_ext_regs {
PERF_REG_X86_ZMM30,
PERF_REG_X86_ZMM31,
+ /* shadow stack pointer (SSP) */
+ PERF_REG_X86_SSP,
+
PERF_REG_X86_EXT_REGS_64 = PERF_REG_X86_ZMM23,
- PERF_REG_X86_EXT_REGS_MAX = PERF_REG_X86_ZMM31,
+ PERF_REG_X86_EXT_REGS_MAX = PERF_REG_X86_SSP,
};
enum perf_event_x86_ext_reg_size {
@@ -148,6 +151,7 @@ enum perf_event_x86_ext_reg_size {
PERF_X86_EXT_REG_OPMASK_SIZE = 1,
PERF_X86_EXT_REG_ZMMH_SIZE = 4,
PERF_X86_EXT_REG_H16ZMM_SIZE = 8,
+ PERF_X86_EXT_REG_SSP_SIZE = 1,
/* max of PERF_REG_X86_XXX_SIZE */
PERF_X86_EXT_REG_SIZE_MAX = PERF_X86_EXT_REG_H16ZMM_SIZE,
diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c
index d5721ea85c5d..6a5936ed7143 100644
--- a/arch/x86/kernel/perf_regs.c
+++ b/arch/x86/kernel/perf_regs.c
@@ -102,6 +102,11 @@ static u64 perf_ext_reg_value(struct pt_regs *regs, int idx,
idx - PERF_REG_X86_ZMM16,
perf_regs->h16zmm_regs,
PERF_X86_EXT_REG_H16ZMM_SIZE);
+ case PERF_REG_X86_SSP:
+ return __perf_ext_reg_value(ext, ext_size,
+ idx - PERF_REG_X86_SSP,
+ &perf_regs->cet_regs[1],
+ PERF_X86_EXT_REG_SSP_SIZE);
default:
WARN_ON_ONCE(1);
*ext_size = 0;
--
2.38.1
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