| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20250613134943.3186517-10-kan.liang@linux.intel.com>
Date: Fri, 13 Jun 2025 06:49:40 -0700
From: kan.liang@...ux.intel.com
To: peterz@...radead.org,
mingo@...hat.com,
acme@...nel.org,
namhyung@...nel.org,
tglx@...utronix.de,
dave.hansen@...ux.intel.com,
irogers@...gle.com,
adrian.hunter@...el.com,
jolsa@...nel.org,
alexander.shishkin@...ux.intel.com,
linux-kernel@...r.kernel.org
Cc: dapeng1.mi@...ux.intel.com,
ak@...ux.intel.com,
zide.chen@...el.com,
Kan Liang <kan.liang@...ux.intel.com>
Subject: [RFC PATCH 09/12] perf/x86: Add OPMASK in extended regs
From: Kan Liang <kan.liang@...ux.intel.com>
Support OPMASK as the extended registers. It can be configured in the
sample_ext_regs_intr/user.
Only the PMU with PERF_PMU_CAP_EXTENDED_REGS2 supports the feature.
The value can be retrieved via the XSAVES.
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
---
arch/x86/events/core.c | 6 ++++++
arch/x86/events/perf_event.h | 4 ++++
arch/x86/include/asm/perf_event.h | 1 +
arch/x86/include/uapi/asm/perf_regs.h | 13 ++++++++++++-
arch/x86/kernel/perf_regs.c | 5 +++++
5 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 67f62268f063..741e6dfd50a5 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -436,6 +436,7 @@ static void x86_pmu_get_ext_regs(struct x86_perf_regs *perf_regs, u64 mask)
/* The XSAVES instruction always uses the compacted format */
__x86_pmu_get_regs(XFEATURE_MASK_YMM, perf_regs->ymmh_regs, XSAVE_YMM_SIZE);
__x86_pmu_get_regs(XFEATURE_MASK_APX, perf_regs->apx_regs, sizeof(struct apx_state));
+ __x86_pmu_get_regs(XFEATURE_MASK_OPMASK, perf_regs->opmask_regs, sizeof(struct avx_512_opmask_state));
}
static void release_ext_regs_buffers(void)
@@ -465,6 +466,8 @@ static void reserve_ext_regs_buffers(void)
size += XSAVE_YMM_SIZE;
if (x86_pmu.ext_regs_mask & BIT_ULL(X86_EXT_REGS_APX))
size += sizeof(struct apx_state);
+ if (x86_pmu.ext_regs_mask & BIT_ULL(X86_EXT_REGS_OPMASK))
+ size += sizeof(struct avx_512_opmask_state);
/* XSAVE feature requires 64-byte alignment. */
size += 64;
@@ -743,6 +746,7 @@ int x86_pmu_hw_config(struct perf_event *event)
return -EINVAL;
check_ext_regs(X86_EXT_REGS_YMM);
check_ext_regs(X86_EXT_REGS_APX);
+ check_ext_regs(X86_EXT_REGS_OPMASK);
}
}
return x86_setup_perfctr(event);
@@ -1846,6 +1850,8 @@ void x86_pmu_setup_regs_data(struct perf_event *event,
XFEATURE_MASK_YMM, PERF_X86_EXT_REG_YMMH_SIZE);
init_ext_regs_data(X86_EXT_REGS_APX, perf_regs->apx_regs,
XFEATURE_MASK_APX, PERF_X86_EXT_REG_APX_SIZE);
+ init_ext_regs_data(X86_EXT_REGS_OPMASK, perf_regs->opmask_regs,
+ XFEATURE_MASK_OPMASK, PERF_X86_EXT_REG_OPMASK_SIZE);
mask &= ~ignore_mask;
if (mask)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 1c40b5d9c025..c2626dcea1a0 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -691,6 +691,7 @@ enum {
X86_EXT_REGS_XMM = 0,
X86_EXT_REGS_YMM,
X86_EXT_REGS_APX,
+ X86_EXT_REGS_OPMASK,
};
#define PERF_PEBS_DATA_SOURCE_MAX 0x100
@@ -1332,6 +1333,9 @@ static inline int get_num_ext_regs(u64 *ext_regs, unsigned int type)
case X86_EXT_REGS_APX:
mask = GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R16);
return hweight64(ext_regs[0] & mask);
+ case X86_EXT_REGS_OPMASK:
+ mask = GENMASK_ULL(PERF_REG_X86_OPMASK7, PERF_REG_X86_OPMASK0);
+ return hweight64(ext_regs[0] & mask);
default:
return 0;
}
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 9e4d60f3a9a2..4e971f38ff94 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -595,6 +595,7 @@ struct x86_perf_regs {
u64 *xmm_regs;
u64 *ymmh_regs;
u64 *apx_regs;
+ u64 *opmask_regs;
};
extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs);
diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h
index e23fb112faac..b9ec58b98c5e 100644
--- a/arch/x86/include/uapi/asm/perf_regs.h
+++ b/arch/x86/include/uapi/asm/perf_regs.h
@@ -92,12 +92,23 @@ enum perf_event_x86_ext_regs {
PERF_REG_X86_R30,
PERF_REG_X86_R31,
- PERF_REG_X86_EXT_REGS_MAX = PERF_REG_X86_R31,
+ /* OPMASK Registers */
+ PERF_REG_X86_OPMASK0,
+ PERF_REG_X86_OPMASK1,
+ PERF_REG_X86_OPMASK2,
+ PERF_REG_X86_OPMASK3,
+ PERF_REG_X86_OPMASK4,
+ PERF_REG_X86_OPMASK5,
+ PERF_REG_X86_OPMASK6,
+ PERF_REG_X86_OPMASK7,
+
+ PERF_REG_X86_EXT_REGS_MAX = PERF_REG_X86_OPMASK7,
};
enum perf_event_x86_ext_reg_size {
PERF_X86_EXT_REG_YMMH_SIZE = 2,
PERF_X86_EXT_REG_APX_SIZE = 1,
+ PERF_X86_EXT_REG_OPMASK_SIZE = 1,
/* max of PERF_REG_X86_XXX_SIZE */
PERF_X86_EXT_REG_SIZE_MAX = PERF_X86_EXT_REG_YMMH_SIZE,
diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c
index 518497bafdf0..34b94b846f00 100644
--- a/arch/x86/kernel/perf_regs.c
+++ b/arch/x86/kernel/perf_regs.c
@@ -87,6 +87,11 @@ static u64 perf_ext_reg_value(struct pt_regs *regs, int idx,
idx - PERF_REG_X86_R16,
perf_regs->apx_regs,
PERF_X86_EXT_REG_APX_SIZE);
+ case PERF_REG_X86_OPMASK0 ... PERF_REG_X86_OPMASK7:
+ return __perf_ext_reg_value(ext, ext_size,
+ idx - PERF_REG_X86_OPMASK0,
+ perf_regs->opmask_regs,
+ PERF_X86_EXT_REG_OPMASK_SIZE);
default:
WARN_ON_ONCE(1);
*ext_size = 0;
--
2.38.1
Powered by blists - more mailing lists