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Message-ID: <aEw9IVCAtANnLPib@geday>
Date: Fri, 13 Jun 2025 12:00:49 -0300
From: Geraldo Nascimento <geraldogabriel@...il.com>
To: linux-rockchip@...ts.infradead.org
Cc: Shawn Lin <shawn.lin@...k-chips.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Manivannan Sadhasivam <mani@...nel.org>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Heiko Stuebner <heiko@...ech.de>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
linux-phy@...ts.infradead.org, linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC PATCH v4 0/4] PCI: rockchip: Improve quality of driver
On Fri, Jun 13, 2025 at 11:48:27AM -0300, Geraldo Nascimento wrote:
> During a 30-day debugging-run fighting quirky PCIe devices on RK3399
> some quality improvements began to take form and this is my attempt
> at upstreaming it. It will ensure maximum chance of retraining to Gen2
> 5.0GT/s, on all four lanes and plus if anybody is debugging the PHY
> they'll now get real values from TEST_I[3:0] for every TEST_ADDR[4:0]
> without risk of locking up kernel like with present broken async
> strobe TEST_WRITE.
>
> ---
> V3 -> V4: fix TLS setting-up in Link Control and Status Register 2 and
> adjust commit titles
> V2 -> V3: correctly clean-up with standard PCIe defines as per Bjorn's
> suggestion
> V1 -> V2: use standard PCIe defines as suggested by Bjorn
>
> Geraldo Nascimento (4):
> PCI: rockchip: Drop unused custom registers and bitfields
> PCI: rockchip: Set Target Link Speed before retraining
> phy: rockchip-pcie: Enable all four lanes
> phy: rockchip-pcie: Adjust read mask and write
>
> drivers/pci/controller/pcie-rockchip-host.c | 4 ++++
> drivers/pci/controller/pcie-rockchip.h | 11 +----------
> drivers/phy/rockchip/phy-rockchip-pcie.c | 16 +++++++++-------
> 3 files changed, 14 insertions(+), 17 deletions(-)
>
> --
> 2.49.0
>
I somehow have screwed-up threading again. Please ignore. Resending
now.
Geraldo Nascimento
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