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Message-ID: <71968fb3-198f-4334-95ea-30a9dfba1935@intel.com>
Date: Fri, 13 Jun 2025 08:48:23 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: kan.liang@...ux.intel.com, peterz@...radead.org, mingo@...hat.com,
acme@...nel.org, namhyung@...nel.org, tglx@...utronix.de,
dave.hansen@...ux.intel.com, irogers@...gle.com, adrian.hunter@...el.com,
jolsa@...nel.org, alexander.shishkin@...ux.intel.com,
linux-kernel@...r.kernel.org
Cc: dapeng1.mi@...ux.intel.com, ak@...ux.intel.com, zide.chen@...el.com
Subject: Re: [RFC PATCH 07/12] perf/x86: Add YMMH in extended regs
On 6/13/25 06:49, kan.liang@...ux.intel.com wrote:
> size = FXSAVE_SIZE + XSAVE_HDR_SIZE;
>
> + if (x86_pmu.ext_regs_mask & BIT_ULL(X86_EXT_REGS_YMM))
> + size += XSAVE_YMM_SIZE;
Sorry, but this is probably buggy too:
> The value returned by ECX[1] indicates the alignment of state
> component i when the compacted format of the extended region of an
> XSAVE area is used (see Section 13.4.3).
You can't simply stack all the sizes on top of each other. You have to
align some of the components individually to a 64-byte boundary. It
works for the large components because they're multiples of 64 bytes
already.
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