linux-kernel - Re: [PATCH 1/1] arm64: dts: msm: Add eMMC support for qcs8300

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Message-ID: <a033f565-96b0-48ba-b12e-8deee4691f72@oss.qualcomm.com>
Date: Fri, 13 Jun 2025 21:40:02 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Sayali Lokhande <quic_sayalil@...cinc.com>, andersson@...nel.org,
        konradybcio@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-mmc-owner@...r.kernel.org
Subject: Re: [PATCH 1/1] arm64: dts: msm: Add eMMC support for qcs8300

On 6/12/25 11:21 AM, Sayali Lokhande wrote:
> Add eMMC support for qcs8300 board.
> 
> Signed-off-by: Sayali Lokhande <quic_sayalil@...cinc.com>
> ---

[...]

> +		sdhc_1: mmc@...4000 {
> +			compatible = "qcom,sdhci-msm-v5";

This needs a SoC-specific compatible and a corresponding dt-bindings
change (see other soc dtsi files, e.g. x1e80100.dtsi) 

> +			status = "disabled";
> +
> +			reg = <0x0 0x87C4000 0x0 0x1000>,
> +				<0x0 0x87C5000 0x0 0x1000>;

Please align the '<'s across this change

> +			reg-names = "hc", "cqhci";
> +
> +			interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hc_irq", "pwr_irq";
> +
> +			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> +					<&gcc GCC_SDCC1_APPS_CLK>,
> +					<&rpmhcc RPMH_CXO_CLK>;
> +			clock-names = "iface", "core", "xo";
> +			interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>,

0 -> QCOM_ICC_TAG_ALWAYS on this path

> +					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>;

0 -> QCOM_ICC_TAG_ACTIVE_ONLY on this path

> +			interconnect-names = "sdhc-ddr","cpu-sdhc";

one per line, please, also change-wide

Konrad