linux-kernel - [tip: perf/urgent] perf/x86/intel: Fix crashing bug in icl_update_topdown

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Message-ID: <174979800111.406.4606845775414969638.tip-bot2@tip-bot2>
Date: Fri, 13 Jun 2025 07:00:01 -0000
From: "tip-bot2 for Kan Liang" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Vince Weaver <vincent.weaver@...ne.edu>,
 Kan Liang <kan.liang@...ux.intel.com>,
 "Peter Zijlstra (Intel)" <peterz@...radead.org>, x86@...nel.org,
 linux-kernel@...r.kernel.org
Subject: [tip: perf/urgent] perf/x86/intel: Fix crashing bug in
 icl_update_topdown_event

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     e49460a2d03fd8689ce5f7f2d79ff159734ad563
Gitweb:        https://git.kernel.org/tip/e49460a2d03fd8689ce5f7f2d79ff159734ad563
Author:        Kan Liang <kan.liang@...ux.intel.com>
AuthorDate:    Thu, 12 Jun 2025 07:38:18 -07:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Fri, 13 Jun 2025 08:54:21 +02:00

perf/x86/intel: Fix crashing bug in icl_update_topdown_event

The perf_fuzzer found a hard-lock crash on a RaptorLake machine.

  Oops: general protection fault, maybe for address 0xffff89aeceab400: 0000
  CPU: 23 UID: 0 PID: 0 Comm: swapper/23
  Tainted: [W]=WARN
  Hardware name: Dell Inc. Precision 9660/0VJ762
  RIP: 0010:native_read_pmc+0x7/0x40
  Code: cc e8 8d a9 01 00 48 89 03 5b cd cc cc cc cc 0f 1f ...
  RSP: 000:fffb03100273de8 EFLAGS: 00010046
  ....
  Call Trace:
    <TASK>
    icl_update_topdown_event+0x165/0x190
    ? ktime_get+0x38/0xd0
    intel_pmu_read_event+0xf9/0x210
    __perf_event_read+0xf9/0x210

The CPUs 16-23 are E-core CPUs that don't support perf metrics feature.
The icl_update_topdown_event() should not be invoked.

It's an regression of the commit f9bdf1f95339 ("perf/x86/intel: Avoid
disable PMU if !cpuc->enabled in sample read"). The is_topdown_event()
is mistakenly used to replace the is_topdown_count() to check if the
topdown functions for the perf metrics feature should be invoked.  The
is_topdown_event() only checks the event encoding. It's possible that
the same encoding 0x0400 is created on an e-core CPU (although there
is no valid event with such encoding on e-core).  The
is_topdown_count() checks the PERF_X86_EVENT_TOPDOWN flag. Only when
the topdown events require the perf metrics magic, the flag is set.

It should be a typo when merging the intel_pmu_auto_reload_read() and
intel_pmu_read_topdown_event() in the commit.

Fixes: f9bdf1f95339 ("perf/x86/intel: Avoid disable PMU if !cpuc->enabled in sample read")
Closes: https://lore.kernel.org/lkml/352f0709-f026-cd45-e60c-60dfd97f73f3@maine.edu/
Reported-by: Vince Weaver <vincent.weaver@...ne.edu>
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Tested-by: Vince Weaver <vincent.weaver@...ne.edu>
Link: https://lore.kernel.org/r/20250612143818.2889040-1-kan.liang@linux.intel.com
---
 arch/x86/events/intel/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 741b229..c2fb729 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2826,7 +2826,7 @@ static void intel_pmu_read_event(struct perf_event *event)
 		 * If the PEBS counters snapshotting is enabled,
 		 * the topdown event is available in PEBS records.
 		 */
-		if (is_topdown_event(event) && !is_pebs_counter_event_group(event))
+		if (is_topdown_count(event) && !is_pebs_counter_event_group(event))
 			static_call(intel_pmu_update_topdown_event)(event, NULL);
 		else
 			intel_pmu_drain_pebs_buffer();