| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20250613055613.866909-4-pritam.sutar@samsung.com>
Date: Fri, 13 Jun 2025 11:26:07 +0530
From: Pritam Manohar Sutar <pritam.sutar@...sung.com>
To: vkoul@...nel.org, kishon@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, alim.akhtar@...sung.com,
andre.draszik@...aro.org, peter.griffin@...aro.org, kauschluss@...root.org,
ivo.ivanov.ivanov1@...il.com, m.szyprowski@...sung.com,
s.nawrocki@...sung.com, pritam.sutar@...sung.com
Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, rosa.pila@...sung.com,
dev.tailor@...sung.com, faraz.ata@...sung.com, muhammed.ali@...sung.com,
selvarasu.g@...sung.com
Subject: [PATCH v3 3/9] arm64: dts: exynos: ExynosAutov920: add USB and
USB-phy nodes
Add USB controller and USB PHY controller nodes for this SoC.
The USB controller has following features:
* Dual Role Device (DRD) controller
* DWC3 compatible
* Supports USB 3.0 host and USB 3.0 device interfaces but phy
controller capability is limited to USB 2.0.
* Supports full-speed (12 Mbps) and high-speed (480 Mbps) modes with
USB device 2.0 interface
* Supports on-chip USB PHY transceiver
* Supports up to 16 bi-directional endpoints (that includes control
endpoint 0)
* Complies with xHCI 1.1 specification
Signed-off-by: Pritam Manohar Sutar <pritam.sutar@...sung.com>
---
.../boot/dts/exynos/exynosautov920-sadk.dts | 37 ++++++
.../arm64/boot/dts/exynos/exynosautov920.dtsi | 108 ++++++++++++++++++
2 files changed, 145 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
index a397f068ed53..984e899a2ebf 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
+++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
@@ -86,3 +86,40 @@ &usi_0 {
&xtcxo {
clock-frequency = <38400000>;
};
+
+/* usb */
+&usbdrd20_phy0 {
+ status = "okay";
+};
+
+&usbdrd20_dwc3_0 {
+ dr_mode = "peripheral";
+};
+
+&usbdrd20_0 {
+ status = "okay";
+};
+
+&usbdrd20_phy1 {
+ status = "okay";
+};
+
+&usbdrd20_dwc3_1 {
+ dr_mode = "peripheral";
+};
+
+&usbdrd20_1 {
+ status = "okay";
+};
+
+&usbdrd20_phy2 {
+ status = "okay";
+};
+
+&usbdrd20_dwc3_2 {
+ dr_mode = "peripheral";
+};
+
+&usbdrd20_2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 2cb8041c8a9f..b1a9d1da47f6 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -1048,6 +1048,114 @@ pinctrl_hsi1: pinctrl@...50000 {
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
};
+ usbdrd20_phy0: phy@...00000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16500000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy1: phy@...10000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16510000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy2: phy@...20000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16520000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_0: usb@...00000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16700000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_0: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy0 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
+ usbdrd20_1: usb@...00000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16800000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_1: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy1 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
+ usbdrd20_2: usb@...00000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16900000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_2: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy2 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
pinctrl_hsi2: pinctrl@...10000 {
compatible = "samsung,exynosautov920-pinctrl";
reg = <0x16c10000 0x10000>;
--
2.34.1
Powered by blists - more mailing lists