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Message-ID: <9455a4e1-6352-4832-ac9f-2816f889c3a4@linaro.org>
Date: Fri, 13 Jun 2025 11:12:26 +0200
From: neil.armstrong@...aro.org
To: Pritam Manohar Sutar <pritam.sutar@...sung.com>, vkoul@...nel.org,
kishon@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
alim.akhtar@...sung.com, andre.draszik@...aro.org, peter.griffin@...aro.org,
kauschluss@...root.org, ivo.ivanov.ivanov1@...il.com,
m.szyprowski@...sung.com, s.nawrocki@...sung.com
Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, rosa.pila@...sung.com,
dev.tailor@...sung.com, faraz.ata@...sung.com, muhammed.ali@...sung.com,
selvarasu.g@...sung.com
Subject: Re: [PATCH v3 9/9] arm64: dts: exynos: ExynosAutov920: add USB and
USB SS combo phy nodes
On 13/06/2025 07:56, Pritam Manohar Sutar wrote:
> Update the USB 3.1 DRD controller and USB31DRD phy nodes to support
> SS combo phy for this soc.
>
> The USB 3.1 DRD controller has the following features:
> * DWC3 compatible
> * compliant with both USB device 3.1 and USB device 2.0 standards
> * compliant with USB host 3.1 and USB host 2.0 standards
> * supports USB device 3.1 and USB device 2.0 interfaces
> * supports USB host 3.1 and USB host 2.0 interfaces
> * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device
> 2.0 interface
> * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface
> * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface
> * single USB port which can be used for USB 3.1 or USB 2.0
> * on-chip USB PHY transceiver
> * supports up to 16 bi-directional endpoints
> * compliant with xHCI 1.1 specification
>
> USB3.1 SSP+(10Gbps) is supported in this commit and SS phy in combo
> phy only supports PIPE3 interface and it is added in index 0 of SS phy.
> UTMI+ and PIPE3 PHY interfaces are specified in "phys" property,
> UTMI+ (index 0 HS phy) and PIPE3 (index 0 SS phy).
>
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@...sung.com>
> ---
> .../arm64/boot/dts/exynos/exynosautov920-sadk.dts | 4 ++++
> arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 15 +++++++++++++--
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
> index a21386bd9af3..40588f7c9998 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
> +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
> @@ -88,6 +88,10 @@ &xtcxo {
> };
>
> /* usb */
> +&usbdrd31_ssphy {
> + status = "okay";
> +};
> +
> &usbdrd31_hsphy {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> index 4efc005cae80..5ee7fad346b9 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> @@ -1048,6 +1048,17 @@ pinctrl_hsi1: pinctrl@...50000 {
> interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + usbdrd31_ssphy: phy@...80000 {
> + compatible = "samsung,exynosautov920-usb31drd-ssphy";
> + reg = <0x16480000 0x0200>;
> + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
> + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
> + clock-names = "phy", "ref";
> + #phy-cells = <1>;
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + status = "disabled";
> + };
> +
> usbdrd31_hsphy: phy@...90000 {
> compatible = "samsung,exynosautov920-usbdrd-hsphy";
> reg = <0x16490000 0x0200>;
> @@ -1109,8 +1120,8 @@ usbdrd31_dwc3: usb@0 {
> <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
> clock-names = "ref", "susp_clk";
> interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
> - phys = <&usbdrd31_hsphy 0>;
> - phy-names = "usb2-phy";
> + phys = <&usbdrd31_hsphy 0>, <&usbdrd31_ssphy 0>;
> + phy-names = "usb2-phy", "usb3-phy";
> snps,has-lpm-erratum;
> snps,dis_u2_susphy_quirk;
> snps,dis_u3_susphy_quirk;
I think at least patch 6 & 9 should be squashed.
Neil
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