linux-kernel - Re: [PATCH 5/8] arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC

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Message-ID: <CA+V-a8s_9WeKJPvyi5-eAVAR2t-z03iC2niFUP-OJgkc-yhD-A@mail.gmail.com>
Date: Fri, 13 Jun 2025 13:43:27 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, linux-renesas-soc@...r.kernel.org, 
	linux-clk@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 5/8] arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC

Hi Geert,

Thank you for the review.

On Thu, Jun 12, 2025 at 3:59 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Add initial SoC DTSI for Renesas RZ/N2H ("R9A09G087") SoC, below are
> > the list of blocks added:
> > - EXT CLKs
> > - 4X CA55
> > - SCIF
> > - CPG
> > - GIC
> > - ARMv8 Timer
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> > @@ -0,0 +1,135 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/N2H SoC
> > + *
> > + * Copyright (C) 2025 Renesas Electronics Corp.
> > + */
> > +
> > +#define RZN2H_PINS_PER_PORT    8
> > +
> > +/*
> > + * Create the pin index from its bank and position numbers and store in
> > + * the upper 16 bits the alternate function identifier
> > + */
> > +#define RZN2H_PORT_PINMUX(b, p, f)     ((b) * RZN2H_PINS_PER_PORT + (p) | ((f) << 16))
> > +
> > +/* Convert a port and pin label to its global pin index */
> > +#define RZN2H_GPIO(port, pin)  ((port) * RZN2H_PINS_PER_PORT + (pin))
>
> These 3 defines belong in the (future) patch that adds the pinctrl node.
>
Ok, I'll make it to the later patch.

> > +       timer {
> > +               compatible = "arm,armv8-timer";
> > +               interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > +                                     <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > +                                     <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > +                                     <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
> > +                                     <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
> > +               interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
>
> Thanks, this brought to my attention that the node in the posted RZ/T2H
> patch is wrong ;-)
>
I have some fixup patches for T2H which apply on v10, maybe I'll post them.

Cheers,
Prabhakar

> > +       };
> > +};
>
> The rest LGTM, so with the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
>