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Message-ID: <aE0rE5hhMM1wNk8R@ysun46-mobl.ccr.corp.intel.com>
Date: Sat, 14 Jun 2025 15:56:03 +0800
From: Yi Sun <yi.sun@...el.com>
To: Fenghua Yu <fenghuay@...dia.com>
CC: <dave.jiang@...el.com>, <vinicius.gomes@...el.com>,
<dmaengine@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<gordon.jin@...el.com>, <anil.s.keshavamurthy@...el.com>,
<philip.lantz@...el.com>
Subject: Re: [PATCH 2/2] dmaengine: idxd: Add Max SGL Size Support for DSA3.0
On 13.06.2025 15:03, Fenghua Yu wrote:
>Hi, Yi,
>
>On 6/13/25 09:18, Yi Sun wrote:
>>Certain DSA 3.0 opcodes, such as Gather copy and Gather reduce requires max
>s/reduce requires/reduce, require/
>>SGL configured for workqueues prior to support these opcodes.
>s/prior to support/prior to supporting/
>>
Get it.
... ...
>> #define IDXD_DSACAP0_OFFSET 0x180
>> union dsacap0_reg {
>>+ struct {
>>+ u64 max_sgl_shift:4;
>>+ u64 max_gr_block_shift:4;
>>+ u64 ops_inter_domain:7;
>>+ u64 rsvd1:17;
>>+ u64 sgl_formats:16;
>>+ u64 max_sg_process:8;
>>+ u64 rsvd2:8;
>>+ };
>
>Ah. The fields are defined here. I would suggest the fields are
>defined in patch 1 because:
>
>1. Reviewer (like me) may get confused when reviewing patch 1 where
>dsacap0 doesn't have any field but is defined a union.
>
>2. There are fields that not max_sgl_shift. So those fields are
>irrelevant to this patch and had better to be define in patch 1.
>
>> u64 bits;
>> };
>
OK, I see. I'll move this definition to patch 1.
Thanks
--Sun, Yi
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