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Message-ID: <202506140931.MWdyPxX1-lkp@intel.com>
Date: Sat, 14 Jun 2025 10:07:51 +0800
From: kernel test robot <lkp@...el.com>
To: Jacky Chou <jacky_chou@...eedtech.com>, bhelgaas@...gle.com,
lpieralisi@...nel.org, kwilczynski@...nel.org, mani@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
joel@....id.au, andrew@...econstruct.com.au, vkoul@...nel.org,
kishon@...nel.org, linus.walleij@...aro.org, p.zabel@...gutronix.de,
linux-aspeed@...ts.ozlabs.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
openbmc@...ts.ozlabs.org, linux-gpio@...r.kernel.org
Cc: llvm@...ts.linux.dev, oe-kbuild-all@...ts.linux.dev,
elbadrym@...gle.com, romlem@...gle.com, anhphan@...gle.com,
wak@...gle.com, yuxiaozhang@...gle.com, BMC-SW@...eedtech.com
Subject: Re: [PATCH 7/7] pci: aspeed: Add ASPEED PCIe host controller driver
Hi Jacky,
kernel test robot noticed the following build warnings:
[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus robh/for-next linusw-pinctrl/devel linusw-pinctrl/for-next linus/master v6.16-rc1 next-20250613]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jacky-Chou/dt-bindings-phy-Add-document-for-ASPEED-PCIe-PHY/20250613-113331
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20250613033001.3153637-8-jacky_chou%40aspeedtech.com
patch subject: [PATCH 7/7] pci: aspeed: Add ASPEED PCIe host controller driver
config: s390-allmodconfig (https://download.01.org/0day-ci/archive/20250614/202506140931.MWdyPxX1-lkp@intel.com/config)
compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250614/202506140931.MWdyPxX1-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202506140931.MWdyPxX1-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/pci/controller/pcie-aspeed.c:481:6: warning: variable 'status' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized]
481 | if (bus->number == 0) {
| ^~~~~~~~~~~~~~~~
drivers/pci/controller/pcie-aspeed.c:541:9: note: uninitialized use occurs here
541 | writel(status, pcie->reg + H2X_CFGE_INT_STS);
| ^~~~~~
drivers/pci/controller/pcie-aspeed.c:481:2: note: remove the 'if' if its condition is always false
481 | if (bus->number == 0) {
| ^~~~~~~~~~~~~~~~~~~~~~~
482 | /* Internal access to bridge */
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
483 | writel(TLP_BYTE_EN(0xf) << 16 | (where & ~3), pcie->reg + H2X_CFGI_TLP);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
484 | writel(CFGI_TLP_FIRE, pcie->reg + H2X_CFGI_CTRL);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
485 | *val = readl(pcie->reg + H2X_CFGI_RET_DATA);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
486 | } else {
| ~~~~~~
drivers/pci/controller/pcie-aspeed.c:474:24: note: initialize the variable 'status' to silence this warning
474 | u32 bdf_offset, status;
| ^
| = 0
drivers/pci/controller/pcie-aspeed.c:573:6: warning: variable 'status' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized]
573 | if (bus->number == 0) {
| ^~~~~~~~~~~~~~~~
drivers/pci/controller/pcie-aspeed.c:622:9: note: uninitialized use occurs here
622 | writel(status, pcie->reg + H2X_CFGE_INT_STS);
| ^~~~~~
drivers/pci/controller/pcie-aspeed.c:573:2: note: remove the 'if' if its condition is always false
573 | if (bus->number == 0) {
| ^~~~~~~~~~~~~~~~~~~~~~~
574 | /* Internal access to bridge */
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
575 | writel(CFGI_WRITE | TLP_BYTE_EN(byte_en) << 16 | (where & ~3),
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
576 | pcie->reg + H2X_CFGI_TLP);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~
577 | writel(val, pcie->reg + H2X_CFGI_WR_DATA);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
578 | writel(CFGI_TLP_FIRE, pcie->reg + H2X_CFGI_CTRL);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
579 | } else {
| ~~~~~~
drivers/pci/controller/pcie-aspeed.c:552:24: note: initialize the variable 'status' to silence this warning
552 | u32 bdf_offset, status, type;
| ^
| = 0
2 warnings generated.
vim +481 drivers/pci/controller/pcie-aspeed.c
469
470 static int aspeed_ast2700_rd_conf(struct pci_bus *bus, unsigned int devfn,
471 int where, int size, u32 *val)
472 {
473 struct aspeed_pcie *pcie = bus->sysdata;
474 u32 bdf_offset, status;
475 u8 type;
476 int ret;
477
478 if ((bus->number == 0 && devfn != 0))
479 return PCIBIOS_DEVICE_NOT_FOUND;
480
> 481 if (bus->number == 0) {
482 /* Internal access to bridge */
483 writel(TLP_BYTE_EN(0xf) << 16 | (where & ~3), pcie->reg + H2X_CFGI_TLP);
484 writel(CFGI_TLP_FIRE, pcie->reg + H2X_CFGI_CTRL);
485 *val = readl(pcie->reg + H2X_CFGI_RET_DATA);
486 } else {
487 if (!aspeed_ast2700_get_link(pcie))
488 return PCIBIOS_DEVICE_NOT_FOUND;
489
490 bdf_offset = aspeed_pcie_get_bdf_offset(bus, devfn, where);
491
492 type = (bus->number == 1) ? PCI_HEADER_TYPE_NORMAL : PCI_HEADER_TYPE_BRIDGE;
493
494 writel(CRG_READ_FMTTYPE(type) | CRG_PAYLOAD_SIZE, pcie->reg + H2X_CFGE_TLP_1ST);
495 writel(AST2700_TX_DESC1_VALUE | (pcie->tx_tag << 8) | TLP_BYTE_EN(0xf),
496 pcie->reg + H2X_CFGE_TLP_NEXT);
497 writel(bdf_offset, pcie->reg + H2X_CFGE_TLP_NEXT);
498 writel(CFGE_TX_IDLE | CFGE_RX_BUSY, pcie->reg + H2X_CFGE_INT_STS);
499 writel(CFGE_TLP_FIRE, pcie->reg + H2X_CFGE_CTRL);
500
501 ret = readl_poll_timeout(pcie->reg + H2X_CFGE_INT_STS, status,
502 (status & CFGE_TX_IDLE), 0, 50);
503 if (ret) {
504 dev_err(pcie->dev,
505 "[%X:%02X:%02X.%02X]CR tx timeout sts: 0x%08x\n",
506 pcie->domain, bus->number, PCI_SLOT(devfn),
507 PCI_FUNC(devfn), status);
508 ret = PCIBIOS_SET_FAILED;
509 *val = ~0;
510 goto out;
511 }
512
513 ret = readl_poll_timeout(pcie->reg + H2X_CFGE_INT_STS, status,
514 (status & CFGE_RX_BUSY), 0, 50000);
515 if (ret) {
516 dev_err(pcie->dev,
517 "[%X:%02X:%02X.%02X]CR rx timeoutsts: 0x%08x\n",
518 pcie->domain, bus->number, PCI_SLOT(devfn),
519 PCI_FUNC(devfn), status);
520 ret = PCIBIOS_SET_FAILED;
521 *val = ~0;
522 goto out;
523 }
524 *val = readl(pcie->reg + H2X_CFGE_RET_DATA);
525 }
526
527 switch (size) {
528 case 1:
529 *val = (*val >> ((where & 3) * 8)) & 0xff;
530 break;
531 case 2:
532 *val = (*val >> ((where & 2) * 8)) & 0xffff;
533 break;
534 case 4:
535 default:
536 break;
537 }
538
539 ret = PCIBIOS_SUCCESSFUL;
540 out:
541 writel(status, pcie->reg + H2X_CFGE_INT_STS);
542 pcie->tx_tag = (pcie->tx_tag + 1) % 0xF;
543 return ret;
544 }
545
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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