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Message-Id: <20250614-axiado-ax3000-soc-and-evaluation-board-support-v1-4-327ab344c16d@axiado.com>
Date: Sat, 14 Jun 2025 18:12:50 -0700
From: Harshit Shah <hshah@...ado.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>, Arnd Bergmann <arnd@...db.de>,
Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-gpio@...r.kernel.org,
soc@...ts.linux.dev, Harshit Shah <hshah@...ado.com>
Subject: [PATCH 4/6] arm64: dts: axiado: Add initial support for AX3000 SoC
and eval board
Add initial device tree support for the AX3000 SoC and its evaluation
platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
Secure Vault, AI Engine and Firewall.
This commit adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
controllers on the AX3000 evaluation board.
Signed-off-by: Harshit Shah <hshah@...ado.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/axiado/Makefile | 2 +
arch/arm64/boot/dts/axiado/ax3000.dtsi | 584 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/axiado/ax3000_evk.dts | 72 ++++
4 files changed, 659 insertions(+)
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += amlogic
subdir-y += apm
subdir-y += apple
subdir-y += arm
+subdir-y += axiado
subdir-y += bitmain
subdir-y += blaize
subdir-y += broadcom
diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..eb5e08ba0f39c32cdbfd586d982849a80da30160
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_AXIADO) += ax3000_evk.dtb
diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..d5d84986d18efe9dfbb446ceee42fc4e4dbf95d0
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
@@ -0,0 +1,584 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
+/ {
+ compatible = "axiado,ax3000";
+ interrupt-parent = <&gic500>;
+
+ aliases {
+ i3c0 = &i3c0;
+ i3c1 = &i3c1;
+ i3c2 = &i3c2;
+ i3c3 = &i3c3;
+ i3c4 = &i3c4;
+ i3c5 = &i3c5;
+ i3c6 = &i3c6;
+ i3c7 = &i3c7;
+ i3c8 = &i3c8;
+ i3c9 = &i3c9;
+ i3c10 = &i3c10;
+ i3c11 = &i3c11;
+ i3c12 = &i3c12;
+ i3c13 = &i3c13;
+ i3c14 = &i3c14;
+ i3c15 = &i3c15;
+ i3c16 = &i3c16;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x3c0013a0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-unified;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+ };
+
+ timer:timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ clocks {
+ refclk: refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ ref_clk: ref_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ clk_ahb: clk_ahb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "clk_ahb";
+ };
+
+ clk_xin: clk_xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "clk_xin";
+ };
+
+ clk_mali: clk_mali {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <500000000>;
+ clock-output-names = "clk_mali";
+ };
+
+ clk_pclk: clk_pclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ clock-output-names = "clk_pclk";
+ };
+
+ spi_clk: spi_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ apb_pclk: apb_pclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic500>;
+ ranges;
+
+ gic500: interrupt-controller@...00000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ reg = <0x00 0x80300000 0x00 0x10000>,
+ <0x00 0x80380000 0x00 0x80000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ };
+
+ uart0: serial@...20000 {
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x00 0x80520000 0x00 0x100>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ uart1: serial@...a0000 {
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x00 0x805A0000 0x00 0x100>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ uart2: serial@...20000 {
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x00 0x80620000 0x00 0x100>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ uart3: serial@...20800 {
+ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x00 0x80520800 0x00 0x100>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &refclk>;
+ status = "disabled";
+ };
+
+ /* GPIO Controller banks 0 - 7 */
+ gpio0: gpio-controller@...00000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x00 0x80500000 0x00 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller@...80000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80580000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio-controller@...00000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80600000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio3: gpio-controller@...80000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80680000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio4: gpio-controller@...00000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80700000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio5: gpio-controller@...80000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80780000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio6: gpio-controller@...00000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80800000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio7: gpio-controller@...80000 {
+ compatible = "cdns,gpio-r1p02";
+ clocks = <&refclk>;
+ reg = <0x00 0x80880000 0x00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ /* I3C Controller 0 - 16 */
+ i3c0: i3c@...00400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80500400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c1: i3c@...00800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80500800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c2: i3c@...80400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80580400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c3: i3c@...80800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80580800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c4: i3c@...00400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80600400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c5: i3c@...00800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80600800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c6: i3c@...80400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80680400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c7: i3c@...80800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80680800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c8: i3c@...00400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80700400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c9: i3c@...00800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80700800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c10: i3c@...80400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80780400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c11: i3c@...80800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80780800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c12: i3c@...00400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80800400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c13: i3c@...00800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80800800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c14: i3c@...80400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80880400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c15: i3c@...80800 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80880800 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c16: i3c@...20400 {
+ compatible = "cdns,i3c-master";
+ clocks = <&refclk &clk_xin>;
+ clock-names = "pclk", "sysclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ reg = <0x00 0x80620400 0x00 0x400>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ };
+};
diff --git a/arch/arm64/boot/dts/axiado/ax3000_evk.dts b/arch/arm64/boot/dts/axiado/ax3000_evk.dts
new file mode 100644
index 0000000000000000000000000000000000000000..0a183695e857a3a1e722ea6b7bee388bf650f0a3
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000_evk.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ax3000.dtsi"
+
+/ {
+ model = "Axiado AX3000 EVK";
+ compatible = "axiado,ax3000_evk", "axiado,ax3000";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ bootargs = "console=ttyPS3,115200 earlyprintk nr_cpus=4 earlycon";
+ stdout-path = "serial3:115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ /* Cortex-A53 will use following memory map */
+ reg = <0x00000000 0x3D000000 0x00000000 0x23000000>,
+ <0x00000004 0x00000000 0x00000000 0x80000000>;
+ };
+};
+
+/* GPIO bank 0 - 7 */
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&gpio6 {
+ status = "okay";
+};
+
+&gpio7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
--
2.25.1
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