linux-kernel - Re: [PATCH v2] net: dsa: mv88e6xxx: fix external smi for mv88e6176

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Message-ID: <c43d06e3-76a2-46d4-a047-3ab647016e22@lunn.ch>
Date: Mon, 16 Jun 2025 21:20:27 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Robert Cross <quantumcross@...il.com>
Cc: bpf@...r.kernel.org, davem@...emloft.net, edumazet@...gle.com,
	kuba@...nel.org, linux-kernel@...r.kernel.org,
	netdev@...r.kernel.org, olteanv@...il.com, pabeni@...hat.com
Subject: Re: [PATCH v2] net: dsa: mv88e6xxx: fix external smi for mv88e6176

On Mon, Jun 16, 2025 at 03:12:14PM -0400, Robert Cross wrote:
> > The MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL bit is reserved on the 6352
> > family.
> 
> Indeed it is...
> 
> > You are not understanding what i'm saying. This family has a single
> > MDIO bus controller. That controller is used by both the internal PHY
> > devices, plus there are two pins on the chip for external PHYs.
> >
> > All the PHYs will appear on that one MDIO bus controller.
> 
> So you're saying that if I removed my hack that apparently just sets
> this reserved bit, and I take my PHY on port 6 and remove it from
> the mdio_ext { compatible = "marvell,mv88e6xxx-mdio-external"; } entry
> and put it in my mdio { } node it will direct requests to address 6 to
> the external phy via the MDC/MDIO_PHY pins just fine?

Yep.

> I'm guessing it will just automatically enable or disable the external
> SMI pins depending on the state of port 5 which shares pins?

I _think_ you will actually see all MDIO transactions on the external
pins. SolidRun got one of their board designs wrong, and put an
external PHY on the same address as an internal PHY. That results in
both not working because they stomp over each other on the bus.

	Andrew