linux-kernel - Re: [PATCH 2/5] dt-bindings: iommu: verisilicon: Add binding for VSI IOMMU

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Message-ID: <699cd8c660c255ab3cbec8760292ee76b8d3660f.camel@collabora.com>
Date: Mon, 16 Jun 2025 17:19:42 -0400
From: Nicolas Dufresne <nicolas.dufresne@...labora.com>
To: Conor Dooley <conor@...nel.org>, Benjamin Gaignard
	 <benjamin.gaignard@...labora.com>
Cc: joro@...tes.org, will@...nel.org, robin.murphy@....com, robh@...nel.org,
 	krzk+dt@...nel.org, conor+dt@...nel.org, heiko@...ech.de,
 p.zabel@...gutronix.de, 	mchehab@...nel.org, iommu@...ts.linux.dev,
 devicetree@...r.kernel.org, 	linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, 	linux-rockchip@...ts.infradead.org,
 linux-media@...r.kernel.org, 	kernel@...labora.com
Subject: Re: [PATCH 2/5] dt-bindings: iommu: verisilicon: Add binding for
 VSI IOMMU

Hi,

Le lundi 16 juin 2025 à 16:14 +0100, Conor Dooley a écrit :
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: verisilicon,iommu
> 
> You're missing a soc-specific compatible at the very least here, but is
> there really no versioning on the IP at all? I'd be surprised if
> verisilicon only produced exactly one version of an iommu IP.

I've dumped the HW ID (base + 6*4), and it reports this IP as an "MM 1.2.0"
(0x4d4d1200).

Note, all VSI IP for which rockchip did not rewrite the register
interface expose a HW ID register, but the from and location can vary.
This one is following the old school H1/G1/G2 style, using ascii to
idenity the core type. Interesting fact too, the register layout seem
to be the same as the Vivante MMU (which is hidden inside the etnaviv
driver).

I'm fine with having a soc specific compatible, just documenting
some fact I could dump.

cheers,
Nicolas

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