linux-kernel - Re: [PATCH v2 1/2] dt-bindings: fpga: Also describe clock for gpio

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Message-ID: <aE+YmvQGvpB3kx48@yilunxu-OptiPlex-7050>
Date: Mon, 16 Jun 2025 12:07:54 +0800
From: Xu Yilun <yilun.xu@...ux.intel.com>
To: Michal Simek <michal.simek@....com>
Cc: linux-kernel@...r.kernel.org, monstr@...str.eu, michal.simek@...inx.com,
	git@...inx.com, Conor Dooley <conor+dt@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Moritz Fischer <mdf@...nel.org>, Rob Herring <robh@...nel.org>,
	Tom Rix <trix@...hat.com>, Wu Hao <hao.wu@...el.com>,
	Xu Yilun <yilun.xu@...el.com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>,
	"open list:FPGA MANAGER FRAMEWORK" <linux-fpga@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] dt-bindings: fpga: Also describe clock for gpio

On Fri, Jun 13, 2025 at 12:52:46PM +0200, Michal Simek wrote:
> 
> 
> On 6/13/25 12:44, Xu Yilun wrote:
> > On Fri, Jun 13, 2025 at 12:12:52PM +0200, Michal Simek wrote:
> > > Axi gpio is going to have clocks as required property that's why it should
> > > be also described in bindings which are using axi gpio node.
> > > 
> > > Signed-off-by: Michal Simek <michal.simek@....com>
> > > ---
> > > 
> > > Changes in v2:
> > > - New patch to fix reported as issue by the second patch
> > > - https://lore.kernel.org/r/174954437576.4177094.15371626866789542129.robh@kernel.org
> > > 
> > >   Documentation/devicetree/bindings/fpga/fpga-region.yaml | 1 +
> > >   1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.yaml b/Documentation/devicetree/bindings/fpga/fpga-region.yaml
> > > index 77554885a6c4..7d2d3b7aa4b7 100644
> > > --- a/Documentation/devicetree/bindings/fpga/fpga-region.yaml
> > > +++ b/Documentation/devicetree/bindings/fpga/fpga-region.yaml
> > > @@ -316,6 +316,7 @@ examples:
> > >           reg = <0x40000000 0x10000>;
> > >           gpio-controller;
> > >           #gpio-cells = <2>;
> > > +        clocks = <&clk>;
> > 
> > This file is mainly for fpga-region bindings. So I don't think we have
> > to strictly align with the example IP block binding every time it has
> > an update.
> 
> But Rob's script are reporting issue if they are not. Please take a look at
> link above.

I see, then from FPGA side

Reviewed-by: Xu Yilun <yilun.xu@...el.com>
> 
> M