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Message-Id: <20250616-rework-icc-v1-25-bc1326294d71@oss.qualcomm.com>
Date: Mon, 16 Jun 2025 03:28:37 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Georgi Djakov <djakov@...nel.org>, Bjorn Andersson <andersson@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 25/28] interconnect: qcom: sm8550: convert to dynamic IDs
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
---
drivers/interconnect/qcom/sm8550.c | 640 +++++++++++++++++--------------------
drivers/interconnect/qcom/sm8550.h | 138 --------
2 files changed, 292 insertions(+), 486 deletions(-)
diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c
index 39101b4a423c1bb404a80a83eaf1ff96ccbf2bad..8e3993c189685693d75e184bbaad5692bef6375c 100644
--- a/drivers/interconnect/qcom/sm8550.c
+++ b/drivers/interconnect/qcom/sm8550.c
@@ -18,1103 +18,1033 @@
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
-#include "sm8550.h"
+
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup2;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node qxm_sp;
+static struct qcom_icc_node xm_qdss_etr_0;
+static struct qcom_icc_node xm_qdss_etr_1;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qup2_core_master;
+static struct qcom_icc_node qsm_cfg;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_lpass_gemnoc;
+static struct qcom_icc_node qnm_mdsp;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_nsp_gemnoc;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qnm_lpiaon_noc;
+static struct qcom_icc_node qnm_lpass_lpinoc;
+static struct qcom_icc_node qxm_lpinoc_dsp_axim;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_camnoc_hf;
+static struct qcom_icc_node qnm_camnoc_icp;
+static struct qcom_icc_node qnm_camnoc_sf;
+static struct qcom_icc_node qnm_mdp;
+static struct qcom_icc_node qnm_vapss_hcp;
+static struct qcom_icc_node qnm_video;
+static struct qcom_icc_node qnm_video_cv_cpu;
+static struct qcom_icc_node qnm_video_cvp;
+static struct qcom_icc_node qnm_video_v_cpu;
+static struct qcom_icc_node qsm_mnoc_cfg;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node qsm_pcie_anoc_cfg;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node qhm_gic;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qup2_core_slave;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mmcx;
+static struct qcom_icc_node qhs_cpr_mxa;
+static struct qcom_icc_node qhs_cpr_mxc;
+static struct qcom_icc_node qhs_cpr_nspcx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_i2c;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_qup2;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_spss_cfg;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qss_lpass_qtb_cfg;
+static struct qcom_icc_node qss_mnoc_cfg;
+static struct qcom_icc_node qss_nsp_qtb_cfg;
+static struct qcom_icc_node qss_pcie_anoc_cfg;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_tme_cfg;
+static struct qcom_icc_node qss_cfg;
+static struct qcom_icc_node qss_ddrss_cfg;
+static struct qcom_icc_node qxs_boot_imem;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc;
+static struct qcom_icc_node qns_lpass_aggnoc;
+static struct qcom_icc_node qns_lpi_aon_noc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node srvc_pcie_aggre_noc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SM8550_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SM8550_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SM8550_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM8550_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM8550_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM8550_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
- .id = SM8550_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM8550_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM8550_MASTER_IPA,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qxm_sp = {
.name = "qxm_sp",
- .id = SM8550_MASTER_SP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
- .id = SM8550_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
- .id = SM8550_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM8550_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc, NULL },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SM8550_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave, NULL },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SM8550_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave, NULL },
};
static struct qcom_icc_node qup2_core_master = {
.name = "qup2_core_master",
- .id = SM8550_MASTER_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_QUP_CORE_2 },
+ .link_nodes = { &qup2_core_slave, NULL },
};
static struct qcom_icc_node qsm_cfg = {
.name = "qsm_cfg",
- .id = SM8550_MASTER_CNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 44,
- .links = { SM8550_SLAVE_AHB2PHY_SOUTH, SM8550_SLAVE_AHB2PHY_NORTH,
- SM8550_SLAVE_APPSS, SM8550_SLAVE_CAMERA_CFG,
- SM8550_SLAVE_CLK_CTL, SM8550_SLAVE_RBCPR_CX_CFG,
- SM8550_SLAVE_RBCPR_MMCX_CFG, SM8550_SLAVE_RBCPR_MXA_CFG,
- SM8550_SLAVE_RBCPR_MXC_CFG, SM8550_SLAVE_CPR_NSPCX,
- SM8550_SLAVE_CRYPTO_0_CFG, SM8550_SLAVE_CX_RDPM,
- SM8550_SLAVE_DISPLAY_CFG, SM8550_SLAVE_GFX3D_CFG,
- SM8550_SLAVE_I2C, SM8550_SLAVE_IMEM_CFG,
- SM8550_SLAVE_IPA_CFG, SM8550_SLAVE_IPC_ROUTER_CFG,
- SM8550_SLAVE_CNOC_MSS, SM8550_SLAVE_MX_RDPM,
- SM8550_SLAVE_PCIE_0_CFG, SM8550_SLAVE_PCIE_1_CFG,
- SM8550_SLAVE_PDM, SM8550_SLAVE_PIMEM_CFG,
- SM8550_SLAVE_PRNG, SM8550_SLAVE_QDSS_CFG,
- SM8550_SLAVE_QSPI_0, SM8550_SLAVE_QUP_1,
- SM8550_SLAVE_QUP_2, SM8550_SLAVE_SDCC_2,
- SM8550_SLAVE_SDCC_4, SM8550_SLAVE_SPSS_CFG,
- SM8550_SLAVE_TCSR, SM8550_SLAVE_TLMM,
- SM8550_SLAVE_UFS_MEM_CFG, SM8550_SLAVE_USB3_0,
- SM8550_SLAVE_VENUS_CFG, SM8550_SLAVE_VSENSE_CTRL_CFG,
- SM8550_SLAVE_LPASS_QTB_CFG, SM8550_SLAVE_CNOC_MNOC_CFG,
- SM8550_SLAVE_NSP_QTB_CFG, SM8550_SLAVE_PCIE_ANOC_CFG,
- SM8550_SLAVE_QDSS_STM, SM8550_SLAVE_TCU },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_apss, &qhs_camera_cfg,
+ &qhs_clk_ctl, &qhs_cpr_cx,
+ &qhs_cpr_mmcx, &qhs_cpr_mxa,
+ &qhs_cpr_mxc, &qhs_cpr_nspcx,
+ &qhs_crypto0_cfg, &qhs_cx_rdpm,
+ &qhs_display_cfg, &qhs_gpuss_cfg,
+ &qhs_i2c, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_mss_cfg, &qhs_mx_rdpm,
+ &qhs_pcie0_cfg, &qhs_pcie1_cfg,
+ &qhs_pdm, &qhs_pimem_cfg,
+ &qhs_prng, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup1,
+ &qhs_qup2, &qhs_sdc2,
+ &qhs_sdc4, &qhs_spss_cfg,
+ &qhs_tcsr, &qhs_tlmm,
+ &qhs_ufs_mem_cfg, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
+ &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg,
+ &xs_qdss_stm, &xs_sys_tcu_cfg, NULL },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SM8550_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 6,
- .links = { SM8550_SLAVE_AOSS, SM8550_SLAVE_TME_CFG,
- SM8550_SLAVE_CNOC_CFG, SM8550_SLAVE_DDRSS_CFG,
- SM8550_SLAVE_BOOT_IMEM, SM8550_SLAVE_IMEM },
+ .link_nodes = { &qhs_aoss, &qhs_tme_cfg,
+ &qss_cfg, &qss_ddrss_cfg,
+ &qxs_boot_imem, &qxs_imem, NULL },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SM8550_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8550_SLAVE_PCIE_0, SM8550_SLAVE_PCIE_1 },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1, NULL },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SM8550_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SM8550_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SM8550_MASTER_APPSS_PROC,
.channels = 3,
.buswidth = 32,
- .num_links = 3,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
- SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SM8550_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_lpass_gemnoc = {
.name = "qnm_lpass_gemnoc",
- .id = SM8550_MASTER_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
- SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mdsp = {
.name = "qnm_mdsp",
- .id = SM8550_MASTER_MSS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
- SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM8550_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM8550_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_nsp_gemnoc = {
.name = "qnm_nsp_gemnoc",
- .id = SM8550_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 2,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SM8550_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc, NULL },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM8550_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 3,
- .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC,
- SM8550_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie, NULL },
};
static struct qcom_icc_node qnm_lpiaon_noc = {
.name = "qnm_lpiaon_noc",
- .id = SM8550_MASTER_LPIAON_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_LPASS_GEM_NOC },
+ .link_nodes = { &qns_lpass_ag_noc_gemnoc, NULL },
};
static struct qcom_icc_node qnm_lpass_lpinoc = {
.name = "qnm_lpass_lpinoc",
- .id = SM8550_MASTER_LPASS_LPINOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC },
+ .link_nodes = { &qns_lpass_aggnoc, NULL },
};
static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
.name = "qxm_lpinoc_dsp_axim",
- .id = SM8550_MASTER_LPASS_PROC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_LPICX_NOC_LPIAON_NOC },
+ .link_nodes = { &qns_lpi_aon_noc, NULL },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM8550_MASTER_LLCC,
.channels = 4,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_EBI1 },
+ .link_nodes = { &ebi, NULL },
};
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
- .id = SM8550_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
- .id = SM8550_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
- .id = SM8550_MASTER_CAMNOC_SF,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_mdp = {
.name = "qnm_mdp",
- .id = SM8550_MASTER_MDP,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf, NULL },
};
static struct qcom_icc_node qnm_vapss_hcp = {
.name = "qnm_vapss_hcp",
- .id = SM8550_MASTER_CDSP_HCP,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video = {
.name = "qnm_video",
- .id = SM8550_MASTER_VIDEO,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cv_cpu = {
.name = "qnm_video_cv_cpu",
- .id = SM8550_MASTER_VIDEO_CV_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
- .id = SM8550_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
- .id = SM8550_MASTER_VIDEO_V_PROC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf, NULL },
};
static struct qcom_icc_node qsm_mnoc_cfg = {
.name = "qsm_mnoc_cfg",
- .id = SM8550_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc, NULL },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = SM8550_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qsm_pcie_anoc_cfg = {
.name = "qsm_pcie_anoc_cfg",
- .id = SM8550_MASTER_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_SERVICE_PCIE_ANOC },
+ .link_nodes = { &srvc_pcie_aggre_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SM8550_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SM8550_MASTER_PCIE_1,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc, NULL },
};
static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
- .id = SM8550_MASTER_GIC_AHB,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM8550_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM8550_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf, NULL },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM8550_MASTER_GIC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc, NULL },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM8550_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc, NULL },
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM8550_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc, NULL },
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SM8550_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SM8550_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qup2_core_slave = {
.name = "qup2_core_slave",
- .id = SM8550_SLAVE_QUP_CORE_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SM8550_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SM8550_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SM8550_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM8550_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM8550_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SM8550_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mmcx = {
.name = "qhs_cpr_mmcx",
- .id = SM8550_SLAVE_RBCPR_MMCX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mxa = {
.name = "qhs_cpr_mxa",
- .id = SM8550_SLAVE_RBCPR_MXA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_mxc = {
.name = "qhs_cpr_mxc",
- .id = SM8550_SLAVE_RBCPR_MXC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cpr_nspcx = {
.name = "qhs_cpr_nspcx",
- .id = SM8550_SLAVE_CPR_NSPCX,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM8550_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SM8550_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM8550_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM8550_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_i2c = {
.name = "qhs_i2c",
- .id = SM8550_SLAVE_I2C,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM8550_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM8550_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SM8550_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SM8550_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = SM8550_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SM8550_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SM8550_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SM8550_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SM8550_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SM8550_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM8550_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SM8550_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SM8550_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_qup2 = {
.name = "qhs_qup2",
- .id = SM8550_SLAVE_QUP_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM8550_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SM8550_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_spss_cfg = {
.name = "qhs_spss_cfg",
- .id = SM8550_SLAVE_SPSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM8550_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SM8550_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM8550_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM8550_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM8550_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM8550_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_lpass_qtb_cfg = {
.name = "qss_lpass_qtb_cfg",
- .id = SM8550_SLAVE_LPASS_QTB_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_mnoc_cfg = {
.name = "qss_mnoc_cfg",
- .id = SM8550_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qsm_mnoc_cfg, NULL },
};
static struct qcom_icc_node qss_nsp_qtb_cfg = {
.name = "qss_nsp_qtb_cfg",
- .id = SM8550_SLAVE_NSP_QTB_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_pcie_anoc_cfg = {
.name = "qss_pcie_anoc_cfg",
- .id = SM8550_SLAVE_PCIE_ANOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_MASTER_PCIE_ANOC_CFG },
+ .link_nodes = { &qsm_pcie_anoc_cfg, NULL },
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM8550_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM8550_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM8550_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
- .id = SM8550_SLAVE_TME_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qss_cfg = {
.name = "qss_cfg",
- .id = SM8550_SLAVE_CNOC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 1,
- .links = { SM8550_MASTER_CNOC_CFG },
+ .link_nodes = { &qsm_cfg, NULL },
};
static struct qcom_icc_node qss_ddrss_cfg = {
.name = "qss_ddrss_cfg",
- .id = SM8550_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
- .id = SM8550_SLAVE_BOOT_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM8550_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SM8550_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SM8550_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 16,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SM8550_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc, NULL },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM8550_SLAVE_LLCC,
.channels = 4,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_LLCC },
+ .link_nodes = { &llcc_mc, NULL },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SM8550_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie, NULL },
};
static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
.name = "qns_lpass_ag_noc_gemnoc",
- .id = SM8550_SLAVE_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_LPASS_GEM_NOC },
+ .link_nodes = { &qnm_lpass_gemnoc, NULL },
};
static struct qcom_icc_node qns_lpass_aggnoc = {
.name = "qns_lpass_aggnoc",
- .id = SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_LPIAON_NOC },
+ .link_nodes = { &qnm_lpiaon_noc, NULL },
};
static struct qcom_icc_node qns_lpi_aon_noc = {
.name = "qns_lpi_aon_noc",
- .id = SM8550_SLAVE_LPICX_NOC_LPIAON_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_LPASS_LPINOC },
+ .link_nodes = { &qnm_lpass_lpinoc, NULL },
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM8550_SLAVE_EBI1,
.channels = 4,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM8550_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf, NULL },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SM8550_SLAVE_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf, NULL },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM8550_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SM8550_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
- .num_links = 1,
- .links = { SM8550_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_nsp_gemnoc, NULL },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SM8550_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie, NULL },
};
static struct qcom_icc_node srvc_pcie_aggre_noc = {
.name = "srvc_pcie_aggre_noc",
- .id = SM8550_SLAVE_SERVICE_PCIE_ANOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
+ .link_nodes = { NULL },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SM8550_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
- .num_links = 1,
- .links = { SM8550_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc, NULL },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM8550_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
- .num_links = 1,
- .links = { SM8550_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf, NULL },
};
static struct qcom_icc_bcm bcm_acv = {
@@ -1277,6 +1207,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_aggre1_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
@@ -1300,6 +1231,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_aggre2_noc = {
+ .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1322,6 +1254,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8550_clk_virt = {
+ .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1382,6 +1315,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_config_noc = {
+ .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1406,6 +1340,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
};
static const struct qcom_icc_desc sm8550_cnoc_main = {
+ .alloc_dyn_id = true,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
@@ -1436,6 +1371,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_gem_noc = {
+ .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1451,6 +1387,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_lpass_ag_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -1467,6 +1404,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
@@ -1482,6 +1420,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = {
+ .alloc_dyn_id = true,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
.bcms = lpass_lpicx_noc_bcms,
@@ -1499,6 +1438,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8550_mc_virt = {
+ .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1527,6 +1467,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_mmss_noc = {
+ .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1543,6 +1484,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_nsp_noc = {
+ .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1562,6 +1504,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_pcie_anoc = {
+ .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1585,6 +1528,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8550_system_noc = {
+ .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
diff --git a/drivers/interconnect/qcom/sm8550.h b/drivers/interconnect/qcom/sm8550.h
deleted file mode 100644
index c9b2986e129337c8b8e0dec208b950bea20d213f..0000000000000000000000000000000000000000
--- a/drivers/interconnect/qcom/sm8550.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * SM8450 interconnect IDs
- *
- * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021, Linaro Limited
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H
-#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H
-
-#define SM8550_MASTER_A1NOC_SNOC 0
-#define SM8550_MASTER_A2NOC_SNOC 1
-#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2
-#define SM8550_MASTER_APPSS_PROC 3
-#define SM8550_MASTER_CAMNOC_HF 4
-#define SM8550_MASTER_CAMNOC_ICP 5
-#define SM8550_MASTER_CAMNOC_SF 6
-#define SM8550_MASTER_CDSP_HCP 7
-#define SM8550_MASTER_CDSP_PROC 8
-#define SM8550_MASTER_CNOC_CFG 9
-#define SM8550_MASTER_CNOC_MNOC_CFG 10
-#define SM8550_MASTER_COMPUTE_NOC 11
-#define SM8550_MASTER_CRYPTO 12
-#define SM8550_MASTER_GEM_NOC_CNOC 13
-#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14
-#define SM8550_MASTER_GFX3D 15
-#define SM8550_MASTER_GIC 16
-#define SM8550_MASTER_GIC_AHB 17
-#define SM8550_MASTER_GPU_TCU 18
-#define SM8550_MASTER_IPA 19
-#define SM8550_MASTER_LLCC 20
-#define SM8550_MASTER_LPASS_GEM_NOC 21
-#define SM8550_MASTER_LPASS_LPINOC 22
-#define SM8550_MASTER_LPASS_PROC 23
-#define SM8550_MASTER_LPIAON_NOC 24
-#define SM8550_MASTER_MDP 25
-#define SM8550_MASTER_MNOC_HF_MEM_NOC 26
-#define SM8550_MASTER_MNOC_SF_MEM_NOC 27
-#define SM8550_MASTER_MSS_PROC 28
-#define SM8550_MASTER_PCIE_0 29
-#define SM8550_MASTER_PCIE_1 30
-#define SM8550_MASTER_PCIE_ANOC_CFG 31
-#define SM8550_MASTER_QDSS_BAM 32
-#define SM8550_MASTER_QDSS_ETR 33
-#define SM8550_MASTER_QDSS_ETR_1 34
-#define SM8550_MASTER_QSPI_0 35
-#define SM8550_MASTER_QUP_1 36
-#define SM8550_MASTER_QUP_2 37
-#define SM8550_MASTER_QUP_CORE_0 38
-#define SM8550_MASTER_QUP_CORE_1 39
-#define SM8550_MASTER_QUP_CORE_2 40
-#define SM8550_MASTER_SDCC_2 41
-#define SM8550_MASTER_SDCC_4 42
-#define SM8550_MASTER_SNOC_GC_MEM_NOC 43
-#define SM8550_MASTER_SNOC_SF_MEM_NOC 44
-#define SM8550_MASTER_SP 45
-#define SM8550_MASTER_SYS_TCU 46
-#define SM8550_MASTER_UFS_MEM 47
-#define SM8550_MASTER_USB3_0 48
-#define SM8550_MASTER_VIDEO 49
-#define SM8550_MASTER_VIDEO_CV_PROC 50
-#define SM8550_MASTER_VIDEO_PROC 51
-#define SM8550_MASTER_VIDEO_V_PROC 52
-#define SM8550_SLAVE_A1NOC_SNOC 53
-#define SM8550_SLAVE_A2NOC_SNOC 54
-#define SM8550_SLAVE_AHB2PHY_NORTH 55
-#define SM8550_SLAVE_AHB2PHY_SOUTH 56
-#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57
-#define SM8550_SLAVE_AOSS 58
-#define SM8550_SLAVE_APPSS 59
-#define SM8550_SLAVE_BOOT_IMEM 60
-#define SM8550_SLAVE_CAMERA_CFG 61
-#define SM8550_SLAVE_CDSP_MEM_NOC 62
-#define SM8550_SLAVE_CLK_CTL 63
-#define SM8550_SLAVE_CNOC_CFG 64
-#define SM8550_SLAVE_CNOC_MNOC_CFG 65
-#define SM8550_SLAVE_CNOC_MSS 66
-#define SM8550_SLAVE_CPR_NSPCX 67
-#define SM8550_SLAVE_CRYPTO_0_CFG 68
-#define SM8550_SLAVE_CX_RDPM 69
-#define SM8550_SLAVE_DDRSS_CFG 70
-#define SM8550_SLAVE_DISPLAY_CFG 71
-#define SM8550_SLAVE_EBI1 72
-#define SM8550_SLAVE_GEM_NOC_CNOC 73
-#define SM8550_SLAVE_GFX3D_CFG 74
-#define SM8550_SLAVE_I2C 75
-#define SM8550_SLAVE_IMEM 76
-#define SM8550_SLAVE_IMEM_CFG 77
-#define SM8550_SLAVE_IPA_CFG 78
-#define SM8550_SLAVE_IPC_ROUTER_CFG 79
-#define SM8550_SLAVE_LLCC 80
-#define SM8550_SLAVE_LPASS_GEM_NOC 81
-#define SM8550_SLAVE_LPASS_QTB_CFG 82
-#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83
-#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84
-#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85
-#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86
-#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87
-#define SM8550_SLAVE_MX_RDPM 88
-#define SM8550_SLAVE_NSP_QTB_CFG 89
-#define SM8550_SLAVE_PCIE_0 90
-#define SM8550_SLAVE_PCIE_0_CFG 91
-#define SM8550_SLAVE_PCIE_1 92
-#define SM8550_SLAVE_PCIE_1_CFG 93
-#define SM8550_SLAVE_PCIE_ANOC_CFG 94
-#define SM8550_SLAVE_PDM 95
-#define SM8550_SLAVE_PIMEM_CFG 96
-#define SM8550_SLAVE_PRNG 97
-#define SM8550_SLAVE_QDSS_CFG 98
-#define SM8550_SLAVE_QDSS_STM 99
-#define SM8550_SLAVE_QSPI_0 100
-#define SM8550_SLAVE_QUP_1 101
-#define SM8550_SLAVE_QUP_2 102
-#define SM8550_SLAVE_QUP_CORE_0 103
-#define SM8550_SLAVE_QUP_CORE_1 104
-#define SM8550_SLAVE_QUP_CORE_2 105
-#define SM8550_SLAVE_RBCPR_CX_CFG 106
-#define SM8550_SLAVE_RBCPR_MMCX_CFG 107
-#define SM8550_SLAVE_RBCPR_MXA_CFG 108
-#define SM8550_SLAVE_RBCPR_MXC_CFG 109
-#define SM8550_SLAVE_SDCC_2 110
-#define SM8550_SLAVE_SDCC_4 111
-#define SM8550_SLAVE_SERVICE_MNOC 112
-#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113
-#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114
-#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115
-#define SM8550_SLAVE_SPSS_CFG 116
-#define SM8550_SLAVE_TCSR 117
-#define SM8550_SLAVE_TCU 118
-#define SM8550_SLAVE_TLMM 119
-#define SM8550_SLAVE_TME_CFG 120
-#define SM8550_SLAVE_UFS_MEM_CFG 121
-#define SM8550_SLAVE_USB3_0 122
-#define SM8550_SLAVE_VENUS_CFG 123
-#define SM8550_SLAVE_VSENSE_CTRL_CFG 124
-
-#endif
--
2.39.5
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