linux-kernel - Re: [PATCH V2 0/3] Add level shifter support for qualcomm SOC's

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <b35d6797-c574-4b85-878d-502fb4b22152@quicinc.com>
Date: Mon, 16 Jun 2025 12:44:00 +0530
From: Sarthak Garg <quic_sartgarg@...cinc.com>
To: Ulf Hansson <ulf.hansson@...aro.org>,
        Konrad Dybcio
	<konrad.dybcio@....qualcomm.com>
CC: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio
	<konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Adrian Hunter
	<adrian.hunter@...el.com>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-mmc@...r.kernel.org>,
        <quic_cang@...cinc.com>, <quic_nguyenb@...cinc.com>,
        <quic_rampraka@...cinc.com>, <quic_pragalla@...cinc.com>,
        <quic_sayalil@...cinc.com>, <quic_nitirawa@...cinc.com>,
        <quic_bhaskarv@...cinc.com>
Subject: Re: [PATCH V2 0/3] Add level shifter support for qualcomm SOC's



On 5/27/2025 8:05 PM, Ulf Hansson wrote:
> On Fri, 23 May 2025 at 20:25, Konrad Dybcio
> <konrad.dybcio@....qualcomm.com> wrote:
>>
>> On 5/23/25 12:57 PM, Sarthak Garg wrote:
>>> Add level shifter support for qualcomm SOC's.
>>>
>>> - Changed from v1
>>>      - As suggested by Krzysztof Kozlowski redesigned logic to use
>>>      compatible property for adding this level shifter support.
>>>      - Addressed Adrian Hunter comments on V1 with resepect to
>>>        checkpatch.
>>>      - Cleared the bits first and then set bits in
>>>        sdhci_msm_execute_tuning as suggested by Adrian Hunter.
>>>      - Upated the if condition logic in msm_set_clock_rate_for_bus_mode
>>>        as suggested by Adrian Hunter.
>>
>> During internal review I suggested we could introduce a generic quirk,
>> perhaps called "max-hs-frequency" which would update this
>> currently-constant value:
>>
>> ---------------- drivers/mmc/core/sd.c ----------------
>> if (status[13] & SD_MODE_HIGH_SPEED)
>>          card->sw_caps.hs_max_dtr = HIGH_SPEED_MAX_DTR;
>> -------------------------------------------------------
>>
>> (50 MHz)
>>
>> which I believe is where it comes from
> 
> I agree that a DT property for the mmc controller would make sense.
> 
> Although, this seems limited to SD UHS-I speed modes, so perhaps
> "max-sd-uhs-frequency" would be a better name for it?
> 
> Kind regards
> Uffe

Sure will update this logic in V3.