linux-kernel - Re: [PATCH v2 2/2] x86/traps: Initialize DR7 by writing its architectural reset value

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Message-ID: <aFFvECpO3lBCjo1l@google.com>
Date: Tue, 17 Jun 2025 06:35:12 -0700
From: Sean Christopherson <seanjc@...gle.com>
To: "Xin Li (Intel)" <xin@...or.com>
Cc: linux-kernel@...r.kernel.org, kvm@...r.kernel.org, tglx@...utronix.de, 
	mingo@...hat.com, bp@...en8.de, dave.hansen@...ux.intel.com, x86@...nel.org, 
	hpa@...or.com, pbonzini@...hat.com, peterz@...radead.org, 
	sohil.mehta@...el.com, brgerst@...il.com, tony.luck@...el.com, 
	fenghuay@...dia.com
Subject: Re: [PATCH v2 2/2] x86/traps: Initialize DR7 by writing its
 architectural reset value

On Tue, Jun 17, 2025, Xin Li (Intel) wrote:
> Initialize DR7 by writing its architectural reset value to ensure
> compliance with the specification.

I wouldn't describe this as a "compliance with the specificiation" issue.  To me,
that implies that clearing bit 10 would somehow be in violation of the SDM, and
that's simply not true.  MOV DR7 won't #GP, the CPU (hopefully) won't catch fire,
etc.

The real motiviation is similar to the DR6 fix: if the architecture changes and
the bit is no longer reserved, at which point clearing it could actually have
meaning.  Something like this?

  Always set bit 10, which is reserved to '1', when "clearing" DR7 so as not
  to trigger unanticipated behavior if said bit is ever unreserved, e.g. as
  a feature enabling flag with inverted polarity.

With a tweaked changelog,

Acked-by: Sean Christopherson <seanjc@...gle.com>