linux-kernel - Re: [PATCH v2 0/3] Relax max-link-speed check to support PCIe Gen5/Gen6

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <d26lnkthpe66s5jg5wufew3p4n6suoldijhcgnihiir5kkjtck@ik5io2tcmx2q>
Date: Tue, 17 Jun 2025 22:19:26 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Hans Zhang <18255117159@....com>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com, 
	krzk+dt@...nel.org, manivannan.sadhasivam@...aro.org, conor+dt@...nel.org, 
	robh@...nel.org, linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org, 
	devicetree@...r.kernel.org
Subject: Re: [PATCH v2 0/3] Relax max-link-speed check to support PCIe
 Gen5/Gen6

On Thu, May 29, 2025 at 10:10:23AM +0800, Hans Zhang wrote:
> This patch series extends PCIe Gen5/Gen6 support for the max-link-speed
> property across device tree bindings and kernel validation logic.
> 
> With PCIe 6.0 now supported in the Linux kernel and industry IP providers
> like Synopsys/Cadence offering PCIe 6.0-compatible IPs, existing device
> tree bindings and checks for max-link-speed (limited to Gen1~Gen4) no
> longer align with hardware capabilities.
> 
> Documentation updates:
> 
> Patch 1/3 extends the PCI host controller binding (pci-bus-common.yaml) to
> explicitly include Gen5/Gen6.
> 
> Patch 2/3 updates the PCI endpoint binding (pci-ep.yaml) with the same
> extension.
> 
> Kernel validation fix:
> 
> Patch 3/3 relaxes the max-link-speed check in of_pci_get_max_link_speed()
> to accept values up to 6, ensuring compatibility with newer generations.
> 
> These changes ensure that device tree configurations for modern PCIe
> controllers (e.g., Synopsys/Cadence IP-based designs) can fully utilize
> Gen5/Gen6 speeds without DT validation errors.
> 
> ---
> In my impression, they have already obtained the relevant certifications.
> 
> e.g.:
> Synopsys:
> https://www.synopsys.com/dw/ipdir.php?ds=dwc_pcie6_controller
> 
> Cadence:
> https://www.cadence.com/en_US/home/tools/silicon-solutions/protocol-ip/pcie-and-compute-express-link/controller-for-pcie-and-cxl/controller-for-pcie.html
> ---
> 
> ---
> Changes for v2:
> - The following files have been deleted:
>   Documentation/devicetree/bindings/pci/pci.txt
> 
>   Update to this file again:
>   dtschema/schemas/pci/pci-bus-common.yaml
> ---
> 
> Hans Zhang (3):
>   dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6
>   dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6

Applied patch 2 to pci/dt-bindings, thanks!

- Mani

>   PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6
> 
>  dtschema/schemas/pci/pci-bus-common.yaml          | 2 +-
>  Documentation/devicetree/bindings/pci/pci.txt     | 5 +++--
>  drivers/pci/of.c                                  | 2 +-
>  3 files changed, 5 insertions(+), 4 deletions(-)
> 
> 
> base-commit: fee3e843b309444f48157e2188efa6818bae85cf
> -- 
> 2.25.1
> 

-- 
மணிவண்ணன் சதாசிவம்