linux-kernel - Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

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Message-ID: <20250617200551.GIaFHKnyPV_XsSjlMP@fat_crate.local>
Date: Tue, 17 Jun 2025 22:05:51 +0200
From: Borislav Petkov <bp@...en8.de>
To: Mikhail Paulyshka <me@...aill.net>
Cc: Mario Limonciello <mario.limonciello@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

On Sat, May 24, 2025 at 05:53:19PM +0300, Mikhail Paulyshka wrote:
> AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an
> error that causes RDSEED to always return 0xffffffff, while RDRAND
> works correctly.
> 
> This patch masks the RDSEED cap for this CPU so that both
> /proc/cpuinfo and direct CPUID read report RDSEED as unavailable.
> 
> 
> v2:
>   * Limit changes to AMD Cyan Skillfish
>   * Replace the runtime RDSEED sanity check with a simple
>     family/model/stepping match
> 
> Signed-off-by: Mikhail Paulyshka <me@...aill.net>
> ---
>  arch/x86/include/asm/msr-index.h       | 1 +
>  arch/x86/kernel/cpu/rdrand.c           | 9 +++++++++
>  tools/arch/x86/include/asm/msr-index.h | 1 +
>  3 files changed, 11 insertions(+)

Does this one work too?

---
From: Mikhail Paulyshka <me@...aill.net>
Date: Sat, 24 May 2025 17:53:19 +0300
Subject: [PATCH] x86/rdrand: Disable RDSEED on AMD Cyan Skillfish

AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an error that
causes RDSEED to always return 0xffffffff, while RDRAND works correctly.

Mask the RDSEED cap for this CPU so that both /proc/cpuinfo and direct CPUID
read report RDSEED as unavailable.

  [ bp: Move to amd.c, massage. ]

Signed-off-by: Mikhail Paulyshka <me@...aill.net>
Signed-off-by: Borislav Petkov (AMD) <bp@...en8.de>
Link: https://lore.kernel.org/20250524145319.209075-1-me@mixaill.net
---
 arch/x86/include/asm/msr-index.h       | 1 +
 arch/x86/kernel/cpu/amd.c              | 7 +++++++
 tools/arch/x86/include/asm/msr-index.h | 1 +
 3 files changed, 9 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b7dded3c8113..5cfb5d74dd5f 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -628,6 +628,7 @@
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0
 #define MSR_AMD_PPIN			0xc00102f1
+#define MSR_AMD64_CPUID_FN_7		0xc0011002
 #define MSR_AMD64_CPUID_FN_1		0xc0011004
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 93da466dfe2c..c2ef5ab4a9e3 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -930,6 +930,13 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
 	init_spectral_chicken(c);
 	fix_erratum_1386(c);
 	zen2_zenbleed_check(c);
+
+	/* Disable RDSEED on AMD Cyan Skillfish because of an error. */
+	if (c->x86_model == 0x47 && c->x86_stepping == 0x0) {
+		clear_cpu_cap(c, X86_FEATURE_RDSEED);
+		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
+		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");
+	}
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index e7d2f460fcc6..2333f4e7bc2f 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -624,6 +624,7 @@
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0
 #define MSR_AMD_PPIN			0xc00102f1
+#define MSR_AMD64_CPUID_FN_7		0xc0011002
 #define MSR_AMD64_CPUID_FN_1		0xc0011004
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022
-- 
2.43.0

-- 
Regards/Gruss,
    Boris.

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