[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ac629489-5086-4cf9-80ed-f5e56b132cf4@linaro.org>
Date: Tue, 17 Jun 2025 11:36:36 +0200
From: neil.armstrong@...aro.org
To: michael.riesch@...labora.com, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Heiko Stuebner <heiko@...ech.de>,
Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Jagan Teki <jagan@...rulasolutions.com>,
Sebastian Reichel <sebastian.reichel@...labora.com>,
Collabora Kernel Team <kernel@...labora.com>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org
Subject: Re: [PATCH 4/5] phy: rockchip: phy-rockchip-inno-csidphy: add support
for rk3588 variant
On 17/06/2025 10:54, Michael Riesch via B4 Relay wrote:
> From: Michael Riesch <michael.riesch@...labora.com>
>
> The Rockchip RK3588 MIPI CSI-2 DPHY can be supported using the existing
> phy-rockchip-inno-csidphy driver, the notable differences being
> - the control bits in the GRF
> - the additional reset line
> Add support for this variant.
>
> Signed-off-by: Michael Riesch <michael.riesch@...labora.com>
> ---
> drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> index 75533d071025..0840be668bfd 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
> @@ -30,6 +30,8 @@
> #define RK3568_GRF_VI_CON0 0x0340
> #define RK3568_GRF_VI_CON1 0x0344
>
> +#define RK3588_CSIDPHY_GRF_CON0 0x0000
> +
> /* PHY */
> #define CSIDPHY_CTRL_LANE_ENABLE 0x00
> #define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6)
> @@ -115,6 +117,12 @@ static const struct dphy_reg rk3568_grf_dphy_regs[] = {
> [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 1, 8),
> };
>
> +static const struct dphy_reg rk3588_grf_dphy_regs[] = {
> + [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 0),
> + [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 4),
> + [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 1, 8),
> +};
> +
> struct hsfreq_range {
> u32 range_h;
> u8 cfg_bit;
> @@ -373,6 +381,15 @@ static const struct dphy_drv_data rk3568_mipidphy_drv_data = {
> .grf_regs = rk3568_grf_dphy_regs,
> };
>
> +static const struct dphy_drv_data rk3588_mipidphy_drv_data = {
> + .pwrctl_offset = -1,
> + .ths_settle_offset = RK3568_CSIDPHY_CLK_WR_THS_SETTLE,
> + .calib_offset = RK3568_CSIDPHY_CLK_CALIB_EN,
> + .hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges,
> + .num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges),
> + .grf_regs = rk3588_grf_dphy_regs,
> +};
> +
> static const struct of_device_id rockchip_inno_csidphy_match_id[] = {
> {
> .compatible = "rockchip,px30-csi-dphy",
> @@ -394,6 +411,10 @@ static const struct of_device_id rockchip_inno_csidphy_match_id[] = {
> .compatible = "rockchip,rk3568-csi-dphy",
> .data = &rk3568_mipidphy_drv_data,
> },
> + {
> + .compatible = "rockchip,rk3588-csi-dphy",
> + .data = &rk3588_mipidphy_drv_data,
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, rockchip_inno_csidphy_match_id);
> @@ -435,7 +456,7 @@ static int rockchip_inno_csidphy_probe(struct platform_device *pdev)
> return PTR_ERR(priv->pclk);
> }
>
> - priv->rst = devm_reset_control_get(dev, "apb");
> + priv->rst = devm_reset_control_array_get(dev, RESET_CONTROL_EXCLUSIVE);
It would be preferable to have the names of the resets lines and use devm_reset_control_bulk_get_exclusive(),
and probably add the reset names to dphy_drv_data
Neil
> if (IS_ERR(priv->rst)) {
> dev_err(dev, "failed to get system reset control\n");
> return PTR_ERR(priv->rst);
>
Powered by blists - more mailing lists