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Message-Id: <20250617021617.2793902-3-quic_ziyuzhan@quicinc.com>
Date: Tue, 17 Jun 2025 10:16:15 +0800
From: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
To: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, jingoohan1@...il.com,
mani@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org,
bhelgaas@...gle.com, johan+linaro@...nel.org, vkoul@...nel.org,
kishon@...nel.org, neil.armstrong@...aro.org, abel.vesa@...aro.org,
kw@...ux.com
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
linux-phy@...ts.infradead.org, qiang.yu@....qualcomm.com,
quic_krichai@...cinc.com, quic_vbadigan@...cinc.com,
Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Subject: [PATCH v2 2/4] dt-bindings: PCI: qcom,pcie-sa8775p: document link_down reset
Each PCIe controller on sa8775p includes 'link_down'reset on hardware,
document it.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
---
.../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
index e3fa232da2ca..b7cae2e556e3 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
@@ -61,11 +61,14 @@ properties:
- const: global
resets:
- maxItems: 1
+ items:
+ - description: PCIe controller reset
+ - description: link_down reset
reset-names:
items:
- - const: pci
+ - const: pci # PCIe core reset
+ - const: link_down # PCIe link down reset
required:
- interconnects
@@ -161,8 +164,10 @@ examples:
power-domains = <&gcc PCIE_0_GDSC>;
- resets = <&gcc GCC_PCIE_0_BCR>;
- reset-names = "pci";
+ resets = <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
--
2.34.1
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