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Message-ID: <20250618144545.GD1613200@noisy.programming.kicks-ass.net>
Date: Wed, 18 Jun 2025 16:45:45 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: "Liang, Kan" <kan.liang@...ux.intel.com>
Cc: Mark Rutland <mark.rutland@....com>,
	"Mi, Dapeng" <dapeng1.mi@...ux.intel.com>, mingo@...hat.com,
	acme@...nel.org, namhyung@...nel.org, tglx@...utronix.de,
	dave.hansen@...ux.intel.com, irogers@...gle.com,
	adrian.hunter@...el.com, jolsa@...nel.org,
	alexander.shishkin@...ux.intel.com, linux-kernel@...r.kernel.org,
	ak@...ux.intel.com, zide.chen@...el.com, broonie@...nel.org
Subject: Re: [RFC PATCH 06/12] perf: Support extension of sample_regs

On Wed, Jun 18, 2025 at 09:52:12AM -0400, Liang, Kan wrote:

> I didn't know we have the alignment requirement for the output.

Perf buffer is in u64 units.

> If so,
> 
> PERF_SAMPLE_SIMD_REGS := {
> 	u64 vectors_mask;
> 	u64 pred_mask;
> 	u64 vector_length:16,
> 	    pred_length:16,
> 	    reserved:32;
> 	u64 data[];
> }

I really don't think we need this complication; XSAVE is a real pain in
the arse, but I think we have enough bits in XSTATE_BV to tell what is
what.


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