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Message-ID: <0d131415-4921-45ac-bcd9-cedff17f34f5@linux.intel.com>
Date: Wed, 18 Jun 2025 11:22:50 -0400
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Mark Rutland <mark.rutland@....com>,
"Mi, Dapeng" <dapeng1.mi@...ux.intel.com>, mingo@...hat.com,
acme@...nel.org, namhyung@...nel.org, tglx@...utronix.de,
dave.hansen@...ux.intel.com, irogers@...gle.com, adrian.hunter@...el.com,
jolsa@...nel.org, alexander.shishkin@...ux.intel.com,
linux-kernel@...r.kernel.org, ak@...ux.intel.com, zide.chen@...el.com,
broonie@...nel.org
Subject: Re: [RFC PATCH 06/12] perf: Support extension of sample_regs
On 2025-06-18 10:45 a.m., Peter Zijlstra wrote:
> On Wed, Jun 18, 2025 at 09:52:12AM -0400, Liang, Kan wrote:
>
>> I didn't know we have the alignment requirement for the output.
>
> Perf buffer is in u64 units.
Sure.
>
>> If so,
>>
>> PERF_SAMPLE_SIMD_REGS := {
>> u64 vectors_mask;
>> u64 pred_mask;
>> u64 vector_length:16,
>> pred_length:16,
>> reserved:32;
>> u64 data[];
>> }
>
> I really don't think we need this complication; XSAVE is a real pain in
> the arse, but I think we have enough bits in XSTATE_BV to tell what is
> what.
I just realized that XSAVE takes the vector as a whole.
It's impossible that XMM0 can be retrieved but XMM1 fails via XSAVE.
I will use the suggested output format.
PERF_SAMPLE_SIMD_REGS := {
u16 nr_vectors;
u16 vector_length;
u16 nr_pred;
u16 pred_length;
u64 data[];
}
Thanks,
Kan
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