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Message-ID: <175021976637.732077.15150240059038030494.b4-ty@kernel.org>
Date: Tue, 17 Jun 2025 23:09:26 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Georgi Djakov <djakov@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
Cc: Odelu Kukatla <quic_okukatla@...cinc.com>,
Jeff Johnson <jeff.johnson@....qualcomm.com>,
Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
Mike Tipton <mdtipton@...cinc.com>,
linux-arm-msm@...r.kernel.org,
linux-pm@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: (subset) [PATCH V11 0/7] Add EPSS L3 provider support on SA8775P SoC
On Tue, 15 Apr 2025 09:53:36 +0000, Raviteja Laggyshetty wrote:
> Add Epoch Subsystem (EPSS) L3 provider support on SA8775P SoCs.
>
> Current interconnect framework is based on static IDs for creating node
> and registering with framework. This becomes a limitation for topologies
> where there are multiple instances of same interconnect provider.
> Modified interconnect framework APIs to create and link icc node with
> dynamic IDs, this will help to overcome the dependency on static IDs.
>
> [...]
Applied, thanks!
[6/7] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider
commit: 6531b4b095dacc3067c91a802e1518f3faad72b4
[7/7] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
commit: 985237d49c4cf0254810b4b8078d240ba9bfc2ec
Best regards,
--
Bjorn Andersson <andersson@...nel.org>
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