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Message-ID: <8ba2f458-4a66-44f6-8528-4654cfe379ff@collabora.com>
Date: Wed, 18 Jun 2025 08:32:25 +0200
From: Michael Riesch <michael.riesch@...labora.com>
To: Neil Armstrong <neil.armstrong@...aro.org>, Rob Herring
<robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Heiko Stuebner <heiko@...ech.de>,
Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Jagan Teki <jagan@...rulasolutions.com>,
Sebastian Reichel <sebastian.reichel@...labora.com>,
Collabora Kernel Team <kernel@...labora.com>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org
Subject: Re: [PATCH 2/5] dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588
variant
Hi Neil,
Thanks for your comments!
On 6/17/25 11:31, neil.armstrong@...aro.org wrote:
> On 17/06/2025 10:54, Michael Riesch via B4 Relay wrote:
>> From: Michael Riesch <michael.riesch@...labora.com>
>>
>> The Rockchip RK3588 variant of the CSI-2 DPHY features two reset lines.
>> Add the variant and allow for the additional reset.
>
> No names for the new resets on the RK3588 ?
I left the names away because TBH I don't see the value in them (in that
case).
Downstream uses reset-names = "srst_csiphy0", "srst_p_csiphy0"; and
there is no better description. One could guess that the second reset
corresponds to "apb" but this is just guessing and we would still have
to guess/find a proper name for the first reset.
Amazingly the mainline driver does not seem to do anything with the
resets (unless I overlooked some implicit magic). Downstream does a
simple reset_control_{assert,deassert} before configuring the PHY. Now
if the different resets are handled in bulk mode, does it really make
sense to address each reset individually?
Best regards,
Michael
>
> Neil
>
>>
>> Signed-off-by: Michael Riesch <michael.riesch@...labora.com>
>> ---
>> .../bindings/phy/rockchip-inno-csi-dphy.yaml | 60 ++++++++++++
>> ++++++++--
>> 1 file changed, 55 insertions(+), 5 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-
>> dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-
>> dphy.yaml
>> index 5ac994b3c0aa..6755738b13ee 100644
>> --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
>> @@ -21,6 +21,7 @@ properties:
>> - rockchip,rk3326-csi-dphy
>> - rockchip,rk3368-csi-dphy
>> - rockchip,rk3568-csi-dphy
>> + - rockchip,rk3588-csi-dphy
>> reg:
>> maxItems: 1
>> @@ -39,18 +40,49 @@ properties:
>> maxItems: 1
>> resets:
>> - items:
>> - - description: exclusive PHY reset line
>> + minItems: 1
>> + maxItems: 2
>> reset-names:
>> - items:
>> - - const: apb
>> + minItems: 1
>> + maxItems: 2
>> rockchip,grf:
>> $ref: /schemas/types.yaml#/definitions/phandle
>> description:
>> Some additional phy settings are access through GRF regs.
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - rockchip,px30-csi-dphy
>> + - rockchip,rk1808-csi-dphy
>> + - rockchip,rk3326-csi-dphy
>> + - rockchip,rk3368-csi-dphy
>> + - rockchip,rk3568-csi-dphy
>> + then:
>> + properties:
>> + resets:
>> + items:
>> + - description: exclusive PHY reset line
>> +
>> + reset-names:
>> + items:
>> + - const: apb
>> +
>> + required:
>> + - reset-names
>> + else:
>> + properties:
>> + resets:
>> + minItems: 2
>> +
>> + reset-names:
>> + minItems: 2
>> +
>> required:
>> - compatible
>> - reg
>> @@ -59,7 +91,6 @@ required:
>> - '#phy-cells'
>> - power-domains
>> - resets
>> - - reset-names
>> - rockchip,grf
>> additionalProperties: false
>> @@ -78,3 +109,22 @@ examples:
>> reset-names = "apb";
>> rockchip,grf = <&grf>;
>> };
>> + - |
>> + #include <dt-bindings/clock/rockchip,rk3588-cru.h>
>> + #include <dt-bindings/reset/rockchip,rk3588-cru.h>
>> +
>> + soc {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + csi_dphy0: phy@...c0000 {
>> + compatible = "rockchip,rk3588-csi-dphy";
>> + reg = <0x0 0xfedc0000 0x0 0x8000>;
>> + clocks = <&cru PCLK_CSIPHY0>;
>> + clock-names = "pclk";
>> + #phy-cells = <0>;
>> + resets = <&cru SRST_CSIPHY0>, <&cru SRST_P_CSIPHY0>;
>> + rockchip,grf = <&csidphy0_grf>;
>> + status = "disabled";
>> + };
>> + };
>>
>
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