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Message-ID: <CALWfF7+G6MRvuSm8a-a0KcPduXz=sYsJT0bB300rAqmtt2w-cg@mail.gmail.com>
Date: Tue, 17 Jun 2025 20:59:28 -0500
From: Jimmy Hon <honyuenkwun@...il.com>
To: Joseph Kogut <joseph.kogut@...il.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Heiko Stuebner <heiko@...ech.de>,
Steve deRosier <derosier@...-sierra.com>, devicetree@...r.kernel.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 3/3] arm64: dts: rockchip: Add support for CM5 IO carrier
On Tue, Jun 17, 2025 at 5:12 PM Joseph Kogut <joseph.kogut@...il.com> wrote:
> +
> +&gmac1 {
> + clock_in_out = "output";
> + phy-handle = <&rgmii_phy1>;
> + phy-mode = "rgmii-id";
> + phy-supply = <&vcc_3v3_s0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac1_miim
> + &gmac1_tx_bus2
> + &gmac1_rx_bus2
> + &gmac1_rgmii_clk
> + &gmac1_rgmii_bus
> + &gmac1_clkinout>;
> + status = "okay";
> +};
> +
Sorry, I meant only the status property should go to the board DTS.
The rest of the gmac1 definition makes sense to put in the SoM dtsi,
since the PHY is on the SoM (as defined in the mdio1 node). So all
the pins between the MAC and PHY will be the same.
Jimmy
>
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