linux-kernel - Re: [PATCH v2 3/4] clk: renesas: r9a09g077-cpg: Add PCLKL core clock

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Message-ID: <CAMuHMdVW8oPiqUqFt573-Db3963Yawm6+sT8DAHTq-64Naegog@mail.gmail.com>
Date: Thu, 19 Jun 2025 17:17:48 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, linux-renesas-soc@...r.kernel.org, 
	linux-clk@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 3/4] clk: renesas: r9a09g077-cpg: Add PCLKL core clock

On Tue, 17 Jun 2025 at 17:58, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Add the Peripheral Module Clock L (PCLKL) for the RZ/T2H (R9A09G077) SoC.
> PCLKL is sourced from PLL1 and runs at 62.5MHz. It is used by various
> low-speed peripherals such as IIC and WDT.
>
> Also update LAST_DT_CORE_CLK to reflect the addition of PCLKL, ensuring
> correct enumeration of core clocks exposed to the DT.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> v1->v2:
> - New patch to add PCLKL core clock.

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-clk for v6.17.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds