linux-kernel - Re: [PATCHv6 01/16] x86/cpu: Enumerate the LASS feature bits

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <25600557-9cd5-406c-9acf-abc163afde2d@infradead.org>
Date: Fri, 20 Jun 2025 09:02:42 -0700
From: Randy Dunlap <rdunlap@...radead.org>
To: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
 Andy Lutomirski <luto@...nel.org>, Thomas Gleixner <tglx@...utronix.de>,
 Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
 Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
 "H. Peter Anvin" <hpa@...or.com>, Peter Zijlstra <peterz@...radead.org>,
 Ard Biesheuvel <ardb@...nel.org>, "Paul E. McKenney" <paulmck@...nel.org>,
 Josh Poimboeuf <jpoimboe@...nel.org>,
 Xiongwei Song <xiongwei.song@...driver.com>, Xin Li <xin3.li@...el.com>,
 "Mike Rapoport (IBM)" <rppt@...nel.org>,
 Brijesh Singh <brijesh.singh@....com>, Michael Roth <michael.roth@....com>,
 Tony Luck <tony.luck@...el.com>, Alexey Kardashevskiy <aik@....com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Jonathan Corbet <corbet@....net>, Sohil Mehta <sohil.mehta@...el.com>,
 Ingo Molnar <mingo@...nel.org>,
 Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
 Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
 Kai Huang <kai.huang@...el.com>, Sandipan Das <sandipan.das@....com>,
 Breno Leitao <leitao@...ian.org>, Rick Edgecombe
 <rick.p.edgecombe@...el.com>, Alexei Starovoitov <ast@...nel.org>,
 Hou Tao <houtao1@...wei.com>, Juergen Gross <jgross@...e.com>,
 Vegard Nossum <vegard.nossum@...cle.com>, Kees Cook <kees@...nel.org>,
 Eric Biggers <ebiggers@...gle.com>, Jason Gunthorpe <jgg@...pe.ca>,
 "Masami Hiramatsu (Google)" <mhiramat@...nel.org>,
 Andrew Morton <akpm@...ux-foundation.org>,
 Luis Chamberlain <mcgrof@...nel.org>, Yuntao Wang <ytcoode@...il.com>,
 Rasmus Villemoes <linux@...musvillemoes.dk>,
 Christophe Leroy <christophe.leroy@...roup.eu>, Tejun Heo <tj@...nel.org>,
 Changbin Du <changbin.du@...wei.com>,
 Huang Shijie <shijie@...amperecomputing.com>,
 Geert Uytterhoeven <geert+renesas@...der.be>,
 Namhyung Kim <namhyung@...nel.org>,
 Arnaldo Carvalho de Melo <acme@...hat.com>, linux-doc@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-efi@...r.kernel.org, linux-mm@...ck.org,
 Yian Chen <yian.chen@...el.com>
Subject: Re: [PATCHv6 01/16] x86/cpu: Enumerate the LASS feature bits

Hi--

On 6/20/25 6:53 AM, Kirill A. Shutemov wrote:
> From: Sohil Mehta <sohil.mehta@...el.com>
> 
> Linear Address Space Separation (LASS) is a security feature that
> intends to prevent malicious virtual address space accesses across
> user/kernel mode.
> 
> Such mode based access protection already exists today with paging and
> features such as SMEP and SMAP. However, to enforce these protections,
> the processor must traverse the paging structures in memory.  Malicious
> software can use timing information resulting from this traversal to
> determine details about the paging structures, and these details may
> also be used to determine the layout of the kernel memory.
> 
> The LASS mechanism provides the same mode-based protections as paging
> but without traversing the paging structures. Because the protections
> enforced by LASS are applied before paging, software will not be able to
> derive paging-based timing information from the various caching
> structures such as the TLBs, mid-level caches, page walker, data caches,
> etc.
> 
> LASS enforcement relies on the typical kernel implementation to divide
> the 64-bit virtual address space into two halves:
>   Addr[63]=0 -> User address space
>   Addr[63]=1 -> Kernel address space
> 
> Any data access or code execution across address spaces typically
> results in a #GP fault.
> 
> The LASS enforcement for kernel data access is dependent on CR4.SMAP
> being set. The enforcement can be disabled by toggling the RFLAGS.AC bit
> similar to SMAP.
> 
> Define the CPU feature bits to enumerate this feature and include
> feature dependencies to reflect the same.
> 
> Co-developed-by: Yian Chen <yian.chen@...el.com>
> Signed-off-by: Yian Chen <yian.chen@...el.com>
> Signed-off-by: Sohil Mehta <sohil.mehta@...el.com>
> Signed-off-by: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@...ux.intel.com>
> ---
>  arch/x86/Kconfig.cpufeatures                |  4 ++++
>  arch/x86/include/asm/cpufeatures.h          |  1 +
>  arch/x86/include/asm/smap.h                 | 22 +++++++++++++++++++--
>  arch/x86/include/uapi/asm/processor-flags.h |  2 ++
>  arch/x86/kernel/cpu/cpuid-deps.c            |  1 +
>  tools/arch/x86/include/asm/cpufeatures.h    |  1 +
>  6 files changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures
> index 250c10627ab3..9574c198fc08 100644
> --- a/arch/x86/Kconfig.cpufeatures
> +++ b/arch/x86/Kconfig.cpufeatures
> @@ -124,6 +124,10 @@ config X86_DISABLED_FEATURE_PCID
>  	def_bool y
>  	depends on !X86_64
>  
> +config X86_DISABLED_FEATURE_LASS
> +	def_bool y
> +	depends on !X86_64

Please explain why this is   !X86_64.
Thanks.

> +
>  config X86_DISABLED_FEATURE_PKU
>  	def_bool y
>  	depends on !X86_INTEL_MEMORY_PROTECTION_KEYS

-- 
~Randy