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Message-ID: <20250620160741.3513940-4-sascha.bischoff@arm.com> Date: Fri, 20 Jun 2025 16:07:51 +0000 From: Sascha Bischoff <Sascha.Bischoff@....com> To: "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "kvmarm@...ts.linux.dev" <kvmarm@...ts.linux.dev>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "kvm@...r.kernel.org" <kvm@...r.kernel.org> CC: nd <nd@....com>, "maz@...nel.org" <maz@...nel.org>, "oliver.upton@...ux.dev" <oliver.upton@...ux.dev>, Joey Gouly <Joey.Gouly@....com>, Suzuki Poulose <Suzuki.Poulose@....com>, "yuzenghui@...wei.com" <yuzenghui@...wei.com>, "will@...nel.org" <will@...nel.org>, "tglx@...utronix.de" <tglx@...utronix.de>, "lpieralisi@...nel.org" <lpieralisi@...nel.org>, Timothy Hayes <Timothy.Hayes@....com> Subject: [PATCH 3/5] arm64/sysreg: Add ICH_VCTLR_EL2 This system register is required to enable/disable V3 legacy mode when running on a GICv5 host. Co-authored-by: Timothy Hayes <timothy.hayes@....com> Signed-off-by: Timothy Hayes <timothy.hayes@....com> Signed-off-by: Sascha Bischoff <sascha.bischoff@....com> --- arch/arm64/tools/sysreg | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index aab58bf4ed9c..dd1ae04eb033 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -4530,6 +4530,12 @@ Field 1 U Field 0 EOI EndSysreg +Sysreg ICH_VCTLR_EL2 3 4 12 11 4 +Res0 63:2 +Field 1 V3 +Field 0 En +EndSysreg + Sysreg CONTEXTIDR_EL2 3 4 13 0 1 Fields CONTEXTIDR_ELx EndSysreg -- 2.34.1
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