[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID:
<SEYPR06MB513414A5AE38EE6749A2902C9D7CA@SEYPR06MB5134.apcprd06.prod.outlook.com>
Date: Fri, 20 Jun 2025 08:20:54 +0000
From: Jacky Chou <jacky_chou@...eedtech.com>
To: Neil Armstrong <neil.armstrong@...aro.org>, "bhelgaas@...gle.com"
<bhelgaas@...gle.com>, "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
"kwilczynski@...nel.org" <kwilczynski@...nel.org>, "mani@...nel.org"
<mani@...nel.org>, "robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
<krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
"joel@....id.au" <joel@....id.au>, "andrew@...econstruct.com.au"
<andrew@...econstruct.com.au>, "vkoul@...nel.org" <vkoul@...nel.org>,
"kishon@...nel.org" <kishon@...nel.org>, "linus.walleij@...aro.org"
<linus.walleij@...aro.org>, "p.zabel@...gutronix.de"
<p.zabel@...gutronix.de>, "linux-aspeed@...ts.ozlabs.org"
<linux-aspeed@...ts.ozlabs.org>, "linux-pci@...r.kernel.org"
<linux-pci@...r.kernel.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "linux-phy@...ts.infradead.org"
<linux-phy@...ts.infradead.org>, "openbmc@...ts.ozlabs.org"
<openbmc@...ts.ozlabs.org>, "linux-gpio@...r.kernel.org"
<linux-gpio@...r.kernel.org>
CC: "elbadrym@...gle.com" <elbadrym@...gle.com>, "romlem@...gle.com"
<romlem@...gle.com>, "anhphan@...gle.com" <anhphan@...gle.com>,
"wak@...gle.com" <wak@...gle.com>, "yuxiaozhang@...gle.com"
<yuxiaozhang@...gle.com>, BMC-SW <BMC-SW@...eedtech.com>
Subject:
回覆: [PATCH 0/7] Add ASPEED PCIe Root Complex support
> > This series has been tested on AST2600/AST2700 platforms and enables
> > PCIe device enumeration and operation.
> >
> > Feedback and review are welcome.
>
> So it seems all PCIe RC code is bundled in a single driver and there's no PCIe
> PHY driver code, is there a reason for that ? If yes I think it should be described
> in the cover letter.
>
Yes, because our design includes the PCIe RC and the PCIe EPs.
The two functions use the same PCIe PHY and are mutually exclusive.
And there are different configurations on RC and EP.
Therefore, we do not use a phy driver to configure our PCIe but use
the phandle of phy syscon to set the RC and EP drivers separately.
I will add more description in next version.
Thanks,
Jacky
Powered by blists - more mailing lists