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Message-ID: <848qlmk6bh.fsf@jogness.linutronix.de>
Date: Fri, 20 Jun 2025 13:26:34 +0206
From: John Ogness <john.ogness@...utronix.de>
To: Yunhui Cui <cuiyunhui@...edance.com>, arnd@...db.de,
andriy.shevchenko@...ux.intel.com, benjamin.larsson@...exis.eu,
cuiyunhui@...edance.com, gregkh@...uxfoundation.org,
heikki.krogerus@...ux.intel.com, ilpo.jarvinen@...ux.intel.com,
jirislaby@...nel.org, jkeeping@...usicbrands.com,
linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org,
markus.mayer@...aro.org, matt.porter@...aro.org, namcao@...utronix.de,
paulmck@...nel.org, pmladek@...e.com, schnelle@...ux.ibm.com,
sunilvl@...tanamicro.com, tim.kryger@...aro.org
Subject: Re: [PATCH v9 3/4] serial: 8250: avoid potential PSLVERR issue
On 2025-06-10, Yunhui Cui <cuiyunhui@...edance.com> wrote:
> When the PSLVERR_RESP_EN parameter is set to 1, reading UART_RX while
> the FIFO is enabled and UART_LSR_DR is not set will generate a PSLVERR
> error.
>
> Failure to check the UART_LSR_DR before reading UART_RX, or the non-
> atomic nature of clearing the FIFO and reading UART_RX, poses
> potential risks that could lead to PSLVERR.
>
> PSLVERR is addressed through two methods. One is to introduce
> serial8250_discard_data() to check whether UART_LSR_DR is set before
> reading UART_RX, thus solving the PSLVERR issue when the FIFO is
> enabled. The other is to place FIFO clearing and reading of UART_RX
> under port->lock.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>
Reviewed-by: John Ogness <john.ogness@...utronix.de>
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