linux-kernel - Re: [RFC PATCH v5 2/4] PCI: rockchip: Set Target Link Speed before retraining

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Message-ID: <562662d4-69ca-4d0e-ad0d-fd8cece417e0@arm.com>
Date: Fri, 20 Jun 2025 13:33:11 +0100
From: Robin Murphy <robin.murphy@....com>
To: Geraldo Nascimento <geraldogabriel@...il.com>,
 linux-rockchip@...ts.infradead.org
Cc: Shawn Lin <shawn.lin@...k-chips.com>,
 Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Krzysztof Wilczyński <kw@...ux.com>,
 Manivannan Sadhasivam <mani@...nel.org>, Rob Herring <robh@...nel.org>,
 Bjorn Helgaas <bhelgaas@...gle.com>, Heiko Stuebner <heiko@...ech.de>,
 Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
 Rick wertenbroek <rick.wertenbroek@...il.com>,
 linux-phy@...ts.infradead.org, linux-pci@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC PATCH v5 2/4] PCI: rockchip: Set Target Link Speed before
 retraining

On 2025-06-13 6:03 pm, Geraldo Nascimento wrote:
> Current code may fail Gen2 retraining if Target Link Speed
> is set to 2.5 GT/s in Link Control and Status Register 2.
> Set it to 5.0 GT/s accordingly.

I have max-link-speed overridden to 2 in my local DTB, and indeed this 
seems to make my NVMe report a 5.0 GT/s link where previously it was 
still downgrading to 2.5, so:

Tested-by: Robin Murphy <robin.murphy@....com>

> Signed-off-by: Geraldo Nascimento <geraldogabriel@...il.com>
> ---
>   drivers/pci/controller/pcie-rockchip-host.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
> index 8489d51e01ca..467e3fc377f7 100644
> --- a/drivers/pci/controller/pcie-rockchip-host.c
> +++ b/drivers/pci/controller/pcie-rockchip-host.c
> @@ -341,6 +341,10 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
>   		 * Enable retrain for gen2. This should be configured only after
>   		 * gen1 finished.
>   		 */
> +		status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2);
> +		status &= ~PCI_EXP_LNKCTL2_TLS;
> +		status |= PCI_EXP_LNKCTL2_TLS_5_0GT;
> +		rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2);
>   		rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2);
>   		status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
>   		status |= PCI_EXP_LNKCTL_RL;