linux-kernel - Re: [PATCH v1 1/7] riscv: helper to parse hart index

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Message-ID: <eb8f5a3b-edee-4525-be69-7a4ad55168a2@ghiti.fr>
Date: Mon, 23 Jun 2025 14:53:06 +0200
From: Alexandre Ghiti <alex@...ti.fr>
To: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
 Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
 Anup Patel <anup@...infault.org>, Chen Wang <unicorn_wang@...look.com>,
 Inochi Amaoto <inochiama@...il.com>, Sunil V L <sunilvl@...tanamicro.com>,
 "Rafael J . Wysocki" <rafael.j.wysocki@...el.com>,
 Ryo Takakura <takakura@...inux.co.jp>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
 linux-riscv@...ts.infradead.org, sophgo@...ts.linux.dev
Subject: Re: [PATCH v1 1/7] riscv: helper to parse hart index

Hi Vladimir,

On 6/9/25 15:47, Vladimir Kondratiev wrote:
> RISC-V APLIC specification defines "hart index" in [1]
> And similar definitions found for ACLINT in [2]
>
> Quote from [1]:
>
> Within a given interrupt domain, each of the domain’s harts has a unique
> index number in the range 0 to 2^14 − 1 (= 16,383). The index number a
> domain associates with a hart may or may not have any relationship to the
> unique hart identifier (“hart ID”) that the RISC-V Privileged
> Architecture assigns to the hart. Two different interrupt domains may
> employ entirely different index numbers for the same set of harts.
>
> Further, [1] says in "4.5 Memory-mapped control region for an
> interrupt domain":
>
> The array of IDC structures may include some for potential hart index
> numbers that are not actual hart index numbers in the domain.
> For example, the first IDC structure is always for hart index 0, but 0 is
> not necessarily a valid index number for any hart in the domain.
>
> Support arbitrary hart indices specified in an optional property
> "riscv,hart-indexes" which is specified as an array of u32 elements, one
> per interrupt target, listing hart indexes in the same order as in
> "interrupts-extended". If this property is not specified, fallback to use
> logical hart indices within the domain.
>
> If property not exist, fall back to logical hart indexes


does not


>
> Link: https://github.com/riscv/riscv-aia [1]
> Link: https://github.com/riscvarchive/riscv-aclint [2]
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>
> ---
>   arch/riscv/include/asm/irq.h |  2 ++
>   arch/riscv/kernel/irq.c      | 34 ++++++++++++++++++++++++++++++++++
>   2 files changed, 36 insertions(+)
>
> diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
> index 7b038f3b7cb0..59c975f750c9 100644
> --- a/arch/riscv/include/asm/irq.h
> +++ b/arch/riscv/include/asm/irq.h
> @@ -22,6 +22,8 @@ void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu);
>   void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));
>   
>   struct fwnode_handle *riscv_get_intc_hwnode(void);
> +int riscv_get_hart_index(struct fwnode_handle *fwnode, u32 logical_index,
> +			 u32 *hart_index);
>   
>   #ifdef CONFIG_ACPI
>   
> diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
> index 9ceda02507ca..efdf505bb776 100644
> --- a/arch/riscv/kernel/irq.c
> +++ b/arch/riscv/kernel/irq.c
> @@ -32,6 +32,40 @@ struct fwnode_handle *riscv_get_intc_hwnode(void)
>   }
>   EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode);
>   
> +/**
> + * riscv_get_hart_index() - get hart index for interrupt delivery
> + * @fwnode: interrupt controller node
> + * @logical_index: index within the "interrupts-extended" property
> + * @hart_index: filled with the hart index to use
> + *
> + * Risc-V uses term "hart index" for its interrupt controllers, for the


s/Risc-V/RISC-V


> + * purpose of the interrupt routing to destination harts.
> + * It may be arbitrary numbers assigned to each destination hart in context
> + * of the particular interrupt domain.
> + *
> + * These numbers encoded in the optional property "riscv,hart-indexes"
> + * that should contain hart index for each interrupt destination in the same
> + * order as in the "interrupts-extended" property. If this property
> + * not exist, it assumed equal to the logical index, i.e. index within the
> + * "interrupts-extended" property.
> + *
> + * Return: error code


This does not add a lot of value, maybe something like that "Return: 0 
on success, a negative error code otherwise"?


> + */
> +int riscv_get_hart_index(struct fwnode_handle *fwnode, u32 logical_index,
> +			 u32 *hart_index)
> +{
> +	static const char *prop_hart_index = "riscv,hart-indexes";
> +	struct device_node *np = to_of_node(fwnode);
> +
> +	if (!np || !of_property_present(np, prop_hart_index)) {
> +		*hart_index = logical_index;
> +		return 0;
> +	}
> +
> +	return of_property_read_u32_index(np, prop_hart_index,
> +					  logical_index, hart_index);
> +}
> +
>   #ifdef CONFIG_IRQ_STACKS
>   #include <asm/irq_stack.h>
>   


With those nits above fixed, you can add:

Acked-by: Alexandre Ghiti <alexghiti@...osinc.com>

Thanks,

Alex