linux-kernel - Re: [PATCH 5/8] dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoC

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Message-ID: <cf9dd904-c24a-4ea3-9689-087efab99d95@quicinc.com>
Date: Mon, 23 Jun 2025 21:19:29 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Krzysztof Kozlowski
	<krzk@...nel.org>,
        Georgi Djakov <djakov@...nel.org>, Rob Herring
	<robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        "Michael
 Turquette" <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        "Philipp Zabel" <p.zabel@...gutronix.de>,
        Anusha Rao
	<quic_anusha@...cinc.com>,
        "Richard Cochran" <richardcochran@...il.com>,
        Konrad Dybcio <konradybcio@...nel.org>,
        Catalin Marinas
	<catalin.marinas@....com>,
        Will Deacon <will@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-pm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <netdev@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <quic_kkumarcs@...cinc.com>,
        <quic_linchen@...cinc.com>, <quic_leiwei@...cinc.com>,
        <quic_suruchia@...cinc.com>, <quic_pavir@...cinc.com>
Subject: Re: [PATCH 5/8] dt-bindings: clock: qcom: Add NSS clock controller
 for IPQ5424 SoC



On 6/21/2025 6:09 PM, Konrad Dybcio wrote:
>>>>      compatible:
>>>> -    const: qcom,ipq9574-nsscc
>>>> +    enum:
>>>> +      - qcom,ipq5424-nsscc
>>>> +      - qcom,ipq9574-nsscc
>>>>        clocks:
>>>>        items:
>>>>          - description: Board XO source
>>>> -      - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
>>>> -      - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
>>>> +      - description: CMN_PLL NSS 1200 MHz or 300 MHZ (Bias PLL cc) clock source
>>>> +      - description: CMN_PLL PPE 353 MHz  or 375 MHZ (Bias PLL ubi nc) clock source
>>> This change means devices are different. Just ocme with your own schema.
>> The NSS clock controller hardware block on the IPQ5424 SoC is identical
>> in design to that of the IPQ9574 SoC. The main difference is in the
>> clock rates for its two parent clocks sourced from the CMN PLL block.
>>
>> Given this, would it be acceptable to update the clock name and its
>> description to use a more generic clock name, such as "nss" and "ppe"
>> instead of the current "nss_1200" and "ppe_353"?
> Because you used those clock_names in the existing ipq9574, you can't
> change them now. You could introduce a separate set of clock_names
> for the new ipq5424 though, but I think it could be useful to drop the
> rate suffix for new additions
> 
> Konrad

OK, Understand, I will add the new separate clock names "nss" and "ppe"
for supporting IPQ5424 SoC and further SoCs with similar design.
Thanks for confirmation.