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Message-ID: <99145cb3-1cb7-43ef-84bd-203616d00681@intel.com>
Date: Mon, 23 Jun 2025 07:51:19 -0700
From: Dave Jiang <dave.jiang@...el.com>
To: Dan Williams <dan.j.williams@...el.com>, linux-cxl@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, Davidlohr Bueso <dave@...olabs.net>,
Jonathan Cameron <jonathan.cameron@...wei.com>,
Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>, Ira Weiny <ira.weiny@...el.com>
Subject: Re: [PATCH v2 4/8] cxl/decoder: Drop pointless locking
On 6/18/25 10:04 PM, Dan Williams wrote:
> cxl_dpa_rwsem coordinates changes to dpa allocation settings for a given
> decoder. cxl_decoder_reset() has no need for a consistent snapshot of the
> dpa settings since it is merely clearing out whatever was there previously.
>
> Otherwise, cxl_region_rwsem protects against 'reset' racing 'setup'.
>
> In preparationg for converting to rw_semaphore_acquire semantics, drop this
> locking.
>
> Cc: Davidlohr Bueso <dave@...olabs.net>
> Cc: Jonathan Cameron <jonathan.cameron@...wei.com>
> Cc: Dave Jiang <dave.jiang@...el.com>
> Cc: Alison Schofield <alison.schofield@...el.com>
> Cc: Vishal Verma <vishal.l.verma@...el.com>
> Cc: Ira Weiny <ira.weiny@...el.com>
> Signed-off-by: Dan Williams <dan.j.williams@...el.com>
Reviewed-by: Dave Jiang <dave.jiang@...el.com>
> ---
> drivers/cxl/core/hdm.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 81556d12e9b8..e9cb34e30248 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -914,7 +914,6 @@ static void cxl_decoder_reset(struct cxl_decoder *cxld)
> "%s: out of order reset, expected decoder%d.%d\n",
> dev_name(&cxld->dev), port->id, port->commit_end);
>
> - down_read(&cxl_dpa_rwsem);
> ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
> ctrl &= ~CXL_HDM_DECODER0_CTRL_COMMIT;
> writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
> @@ -923,7 +922,6 @@ static void cxl_decoder_reset(struct cxl_decoder *cxld)
> writel(0, hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(id));
> writel(0, hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id));
> writel(0, hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id));
> - up_read(&cxl_dpa_rwsem);
>
> cxld->flags &= ~CXL_DECODER_F_ENABLE;
>
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