linux-kernel - Re: [PATCH net-next RFC v2 4/4] riscv: dts: sophgo: Add ethernet configuration for Huashan Pi

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Message-ID: <bd1485c7-e6c3-4360-8e3c-e584ea0b8040@lunn.ch>
Date: Mon, 23 Jun 2025 09:26:43 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Inochi Amaoto <inochiama@...il.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Chen Wang <unicorn_wang@...look.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
	Richard Cochran <richardcochran@...il.com>,
	Alexander Sverdlin <alexander.sverdlin@...il.com>,
	Thomas Bonnefille <thomas.bonnefille@...tlin.com>,
	Yu Yuan <yu.yuan@...u.edu.cn>, Ze Huang <huangze@...t.edu.cn>,
	netdev@...r.kernel.org, devicetree@...r.kernel.org,
	sophgo@...ts.linux.dev, linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org, Yixun Lan <dlan@...too.org>,
	Longbin Li <looong.bin@...il.com>
Subject: Re: [PATCH net-next RFC v2 4/4] riscv: dts: sophgo: Add ethernet
 configuration for Huashan Pi

On Mon, Jun 23, 2025 at 08:30:46AM +0800, Inochi Amaoto wrote:
> Add configuration for ethernet controller on Huashan Pi.
> 
> Signed-off-by: Inochi Amaoto <inochiama@...il.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> index 26b57e15adc1..86f76159c304 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> @@ -55,6 +55,16 @@ &emmc {
>  	non-removable;
>  };
>  
> +&gmac0 {
> +	status = "okay";
> +	phy-handle = <&internal_ephy>;
> +	phy-mode = "internal";
> +};

Since the PHY is internal, it should be part of the SoC .dtsi file,
same as any other peripheral. The board .dts file can then enable it.

    Andrew

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