linux-kernel - Re: [PATCH] arm64: dts: rockchip: use cs-gpios for spi1 on ringneck

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Message-Id: <175064594664.881054.5188113186564000482.robh@kernel.org>
Date: Sun, 22 Jun 2025 21:39:07 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Jakob Unterwurzacher <jakobunt@...il.com>
Cc: Heiko Stuebner <heiko@...ech.de>, linux-rockchip@...ts.infradead.org, 
 linux-kernel@...r.kernel.org, Conor Dooley <conor+dt@...nel.org>, 
 Diederik de Haas <didi.debian@...ow.org>, Johan Jonker <jbx6244@...il.com>, 
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
 Farouk Bouabid <farouk.bouabid@...rry.de>, 
 Jakob Unterwurzacher <jakob.unterwurzacher@...rry.de>, 
 stable@...r.kernel.org, Lukasz Czechowski <lukasz.czechowski@...umatec.com>, 
 Dragan Simic <dsimic@...jaro.org>, 
 Quentin Schulz <quentin.schulz@...rry.de>, 
 Heiko Stuebner <heiko.stuebner@...rry.de>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>
Subject: Re: [PATCH] arm64: dts: rockchip: use cs-gpios for spi1 on
 ringneck


On Fri, 20 Jun 2025 13:35:46 +0200, Jakob Unterwurzacher wrote:
> From: Jakob Unterwurzacher <jakob.unterwurzacher@...rry.de>
> 
> Hardware CS has a very slow rise time of about 6us,
> causing transmission errors when CS does not reach
> high between transaction.
> 
> It looks like it's not driven actively when transitioning
> from low to high but switched to input, so only the CPU
> pull-up pulls it high, slowly. Transitions from high to low
> are fast. On the oscilloscope, CS looks like an irregular sawtooth
> pattern like this:
>                          _____
>               ^         /     |
>       ^      /|        /      |
>      /|     / |       /       |
>     / |    /  |      /        |
> ___/  |___/   |_____/         |___
> 
> With cs-gpios we have a CS rise time of about 20ns, as it should be,
> and CS looks rectangular.
> 
> This fixes the data errors when running a flashcp loop against a
> m25p40 spi flash.
> 
> With the Rockchip 6.1 kernel we see the same slow rise time, but
> for some reason CS is always high for long enough to reach a solid
> high.
> 
> The RK3399 and RK3588 SoCs use the same SPI driver, so we also
> checked our "Puma" (RK3399) and "Tiger" (RK3588) boards.
> They do not have this problem. Hardware CS rise time is good.
> 
> Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard")
> Cc: stable@...r.kernel.org
> Reviewed-by: Quentin Schulz <quentin.schulz@...rry.de>
> Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@...rry.de>
> ---
>  .../boot/dts/rockchip/px30-ringneck.dtsi      | 22 +++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/next-20250619 (exact match)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/rockchip/' for 20250620113549.2900285-1-jakob.unterwurzacher@...rry.de:

arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dtb: spi1: spi1-csn0-gpio: {'rockchip,pins': [[3, 9, 0, 150]], 'phandle': 87} is not of type 'array'
	from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml#
arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dtb: spi1: spi1-csn1-gpio: {'rockchip,pins': [[3, 10, 0, 150]], 'phandle': 88} is not of type 'array'
	from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml#